Duncan Laurie | ba49c09 | 2018-03-27 13:34:40 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2018 Google LLC |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <baseboard/gpio.h> |
| 17 | #include <baseboard/variants.h> |
| 18 | #include <commonlib/helpers.h> |
| 19 | |
| 20 | /* Pad configuration in ramstage */ |
| 21 | /* Leave eSPI pins untouched from default settings */ |
| 22 | static const struct pad_config gpio_table[] = { |
| 23 | /* A0 : RCIN# ==> NC(TP763) */ |
| 24 | PAD_CFG_NC(GPP_A0), |
| 25 | /* A1 : ESPI_IO0 */ |
| 26 | /* A2 : ESPI_IO1 */ |
| 27 | /* A3 : ESPI_IO2 */ |
| 28 | /* A4 : ESPI_IO3 */ |
| 29 | /* A5 : ESPI_CS# */ |
| 30 | /* A6 : SERIRQ ==> NC(TP764) */ |
| 31 | PAD_CFG_NC(GPP_A6), |
| 32 | /* A7 : PIRQA# ==> NC(TP703) */ |
| 33 | PAD_CFG_NC(GPP_A7), |
| 34 | /* A8 : CLKRUN# ==> NC(TP758)) */ |
| 35 | PAD_CFG_NC(GPP_A8), |
| 36 | /* A9 : ESPI_CLK */ |
| 37 | /* A10 : CLKOUT_LPC1 ==> NC */ |
| 38 | PAD_CFG_NC(GPP_A10), |
| 39 | /* A11 : PME# ==> NC(TP726) */ |
| 40 | PAD_CFG_NC(GPP_A11), |
| 41 | /* A12 : BM_BUSY# ==> NC */ |
| 42 | PAD_CFG_NC(GPP_A12), |
| 43 | /* A13 : SUSWARN# ==> SUSWARN_L */ |
| 44 | PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), |
| 45 | /* A14 : ESPI_RESET# */ |
| 46 | /* A15 : SUSACK# ==> SUSACK_L */ |
| 47 | PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), |
| 48 | /* A16 : SD_1P8_SEL ==> NC */ |
| 49 | PAD_CFG_NC(GPP_A16), |
| 50 | /* A17 : SD_PWR_EN# ==> NC */ |
| 51 | PAD_CFG_NC(GPP_A17), |
| 52 | /* A18 : ISH_GP0 ==> ISH_GP0 */ |
| 53 | PAD_CFG_NC(GPP_A18), |
| 54 | /* A19 : ISH_GP1 ==> TRACKPAD_INT_L */ |
| 55 | PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST), |
| 56 | /* A20 : ISH_GP2 ==> ISH_UART0_RXD */ |
| 57 | PAD_CFG_NC(GPP_A20), |
| 58 | /* A21 : ISH_GP3 */ |
| 59 | PAD_CFG_NC(GPP_A21), |
| 60 | /* A22 : ISH_GP4 */ |
| 61 | PAD_CFG_NC(GPP_A22), |
| 62 | /* A23 : ISH_GP5 */ |
| 63 | PAD_CFG_NC(GPP_A23), |
| 64 | |
| 65 | /* B0 : CORE_VID0 ==> NC(TP42) */ |
| 66 | PAD_CFG_NC(GPP_B0), |
| 67 | /* B1 : CORE_VID1 ==> NC(TP43) */ |
| 68 | PAD_CFG_NC(GPP_B1), |
| 69 | /* B2 : VRALERT# ==> NC */ |
| 70 | PAD_CFG_NC(GPP_B2), |
| 71 | /* B3 : CPU_GP2 ==> NC */ |
| 72 | PAD_CFG_NC(GPP_B3), |
| 73 | /* B4 : CPU_GP3 ==> NC */ |
| 74 | PAD_CFG_NC(GPP_B4), |
| 75 | /* B5 : SRCCLKREQ0# ==> NC */ |
| 76 | PAD_CFG_NC(GPP_B5), |
| 77 | /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ |
| 78 | PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), |
| 79 | /* B7 : SRCCLKREQ2# ==> NC */ |
| 80 | PAD_CFG_NC(GPP_B7), |
| 81 | /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ |
| 82 | PAD_CFG_GPO(GPP_B8, 0, RSMRST), |
| 83 | /* B9 : SRCCLKREQ4# ==> NC */ |
| 84 | PAD_CFG_NC(GPP_B9), |
| 85 | /* B10 : SRCCLKREQ5# ==> NC */ |
| 86 | PAD_CFG_NC(GPP_B10), |
| 87 | /* B11 : EXT_PWR_GATE# ==> NC */ |
| 88 | PAD_CFG_NC(GPP_B11), |
| 89 | /* B12 : SLP_S0# ==> SLP_S0_L_G */ |
| 90 | PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 91 | /* B13 : PLTRST# ==> PLT_RST_L */ |
| 92 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 93 | /* B14 : SPKR ==> NC */ |
| 94 | PAD_CFG_NC(GPP_B14), |
| 95 | /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ |
| 96 | PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), |
| 97 | /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ |
| 98 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), |
| 99 | /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ |
| 100 | PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), |
| 101 | /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ |
| 102 | PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), |
| 103 | /* B19 : GSPI1_CS# ==> NC */ |
| 104 | PAD_CFG_NC(GPP_B19), |
| 105 | /* B20 : GSPI1_CLK ==> NC */ |
| 106 | PAD_CFG_NC(GPP_B20), |
| 107 | /* B21 : GSPI1_MISO ==> NC */ |
| 108 | PAD_CFG_NC(GPP_B21), |
| 109 | /* B22 : GSPI1_MOSI ==> NC */ |
| 110 | PAD_CFG_NC(GPP_B22), |
| 111 | /* B23 : SM1ALERT# ==> NC */ |
| 112 | PAD_CFG_NC(GPP_B23), |
| 113 | |
| 114 | /* C0 : SMBCLK ==> NC */ |
| 115 | PAD_CFG_NC(GPP_C0), |
| 116 | /* C1 : SMBDATA ==> NC */ |
| 117 | PAD_CFG_NC(GPP_C1), |
| 118 | /* C2 : SMBALERT# ==> NC */ |
| 119 | PAD_CFG_NC(GPP_C2), |
| 120 | /* C3 : SML0CLK ==> NC */ |
| 121 | PAD_CFG_NC(GPP_C3), |
| 122 | /* C4 : SML0DATA ==> NC */ |
| 123 | PAD_CFG_NC(GPP_C4), |
| 124 | /* C5 : SML0ALERT# ==> NC */ |
| 125 | PAD_CFG_NC(GPP_C5), |
| 126 | /* C6 : SM1CLK ==> EC_IN_RW_OD */ |
| 127 | PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), |
| 128 | /* C7 : SM1DATA ==> NC */ |
| 129 | PAD_CFG_NC(GPP_C7), |
| 130 | /* C8 : UART0_RXD ==> NC */ |
| 131 | PAD_CFG_NC(GPP_C8), |
| 132 | /* C9 : UART0_TXD ==> NC */ |
| 133 | PAD_CFG_NC(GPP_C9), |
| 134 | /* C10 : UART0_RTS# ==> NC */ |
| 135 | PAD_CFG_NC(GPP_C10), |
| 136 | /* C11 : UART0_CTS# ==> NC */ |
| 137 | PAD_CFG_NC(GPP_C11), |
| 138 | /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ |
| 139 | PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), |
| 140 | /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ |
| 141 | PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), |
| 142 | /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */ |
| 143 | PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), |
| 144 | /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */ |
| 145 | PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), |
| 146 | /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_SDA */ |
| 147 | PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), |
| 148 | /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_SCL */ |
| 149 | PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), |
| 150 | /* C18 : I2C1_SDA ==> NC */ |
| 151 | PAD_CFG_NC(GPP_C18), |
| 152 | /* C19 : I2C1_SCL ==> NC */ |
| 153 | PAD_CFG_NC(GPP_C19), |
| 154 | /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ |
| 155 | PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), |
| 156 | /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ |
| 157 | PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), |
| 158 | /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ |
| 159 | PAD_CFG_GPO(GPP_C22, 0, DEEP), |
| 160 | /* C23 : UART2_CTS# ==> PCH_WP */ |
| 161 | PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), |
| 162 | |
| 163 | /* D0 : SPI1_CS# ==> NC */ |
| 164 | PAD_CFG_NC(GPP_D0), |
| 165 | /* D1 : SPI1_CLK ==> TRACKPAD_RESET_1V8_ODL */ |
| 166 | PAD_CFG_GPO(GPP_D1, 0, DEEP), |
| 167 | /* D2 : SPI1_MISO ==> NC */ |
| 168 | PAD_CFG_NC(GPP_D2), |
| 169 | /* D3 : SPI1_MOSI ==> NC */ |
| 170 | PAD_CFG_NC(GPP_D3), |
| 171 | /* D4 : FASHTRIG ==> NC */ |
| 172 | PAD_CFG_NC(GPP_D4), |
| 173 | /* D5 : ISH_I2C0_SDA ==> ISH_I2C0_SDA */ |
| 174 | PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), |
| 175 | /* D6 : ISH_I2C0_SCL ==> ISH_I2C0_SCL */ |
| 176 | PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), |
| 177 | /* D7 : ISH_I2C1_SDA ==> SPKR_IRQ_L */ |
| 178 | PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST), |
| 179 | /* D8 : ISH_I2C1_SCL ==> EN_CAMERA_PWR */ |
| 180 | PAD_CFG_GPO(GPP_D8, 0, DEEP), |
| 181 | /* D9 : ISH_SPI_CS# ==> ISH_SPI_CS_L */ |
| 182 | PAD_CFG_NF_1V8(GPP_D9, NONE, DEEP, NF1), |
| 183 | /* D10 : ISH_SPI_CLK ==> ISH_SPI_CLK */ |
| 184 | PAD_CFG_NF_1V8(GPP_D10, NONE, DEEP, NF1), |
| 185 | /* D11 : ISH_SPI_MISO ==> ISH_SPI_MISO */ |
| 186 | PAD_CFG_NF_1V8(GPP_D11, NONE, DEEP, NF1), |
| 187 | /* D12 : ISH_SPI_MOSI ==> ISH_SPI_MOSI */ |
| 188 | PAD_CFG_NF_1V8(GPP_D12, NONE, DEEP, NF1), |
| 189 | /* D13 : ISH_UART0_RXD ==> ISH_UART0_RXD */ |
| 190 | PAD_CFG_NF_1V8(GPP_D13, NONE, DEEP, NF1), |
| 191 | /* D14 : ISH_UART0_TXD ==> ISH_UART0_TXD */ |
| 192 | PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1), |
| 193 | /* D15 : ISH_UART0_RTS# ==> NC */ |
| 194 | PAD_CFG_NC(GPP_D15), |
| 195 | /* D16 : ISH_UART0_CTS# ==> NC */ |
| 196 | PAD_CFG_NC(GPP_D16), |
| 197 | /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */ |
| 198 | PAD_CFG_GPO(GPP_D17, 0, DEEP), |
| 199 | /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */ |
| 200 | PAD_CFG_GPO(GPP_D18, 0, DEEP), |
| 201 | /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ |
| 202 | PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), |
| 203 | /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ |
| 204 | PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), |
| 205 | /* D21 : SPI1_IO2 ==> NC */ |
| 206 | PAD_CFG_NC(GPP_D21), |
| 207 | /* D22 : SPI1_IO3 ==> NC */ |
| 208 | PAD_CFG_NC(GPP_D22), |
| 209 | /* D23 : I2S_MCLK ==> I2S_MCLK_R */ |
| 210 | PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), |
| 211 | |
| 212 | /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */ |
| 213 | PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), |
| 214 | /* E1 : SATAXPCIE1 ==> NC */ |
| 215 | PAD_CFG_NC(GPP_E1), |
| 216 | /* E2 : SATAXPCIE2 ==> NC */ |
| 217 | PAD_CFG_NC(GPP_E2), |
| 218 | /* E3 : CPU_GP0 ==> NC */ |
| 219 | PAD_CFG_NC(GPP_E3), |
| 220 | /* E4 : SATA_DEVSLP0 ==> NC */ |
| 221 | PAD_CFG_NC(GPP_E4), |
| 222 | /* E5 : SATA_DEVSLP1 ==> NC */ |
| 223 | PAD_CFG_NC(GPP_E5), |
| 224 | /* E6 : SATA_DEVSLP2 ==> NC */ |
| 225 | PAD_CFG_NC(GPP_E6), |
| 226 | /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ |
| 227 | PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), |
| 228 | /* E8 : SATALED# ==> NC */ |
| 229 | PAD_CFG_NC(GPP_E8), |
| 230 | /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ |
| 231 | PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), |
| 232 | /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ |
| 233 | PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), |
| 234 | /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ |
| 235 | PAD_CFG_GPO(GPP_E11, 0, DEEP), |
| 236 | /* E12 : USB2_OC3# ==> NC */ |
| 237 | PAD_CFG_NC(GPP_E12), |
| 238 | /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ |
| 239 | PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), |
| 240 | /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */ |
| 241 | PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), |
| 242 | /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */ |
| 243 | PAD_CFG_GPO(GPP_E15, 1, DEEP), |
| 244 | /* E16 : DDPE_HPD3 ==> NC */ |
| 245 | PAD_CFG_NC(GPP_E16), |
| 246 | /* E17 : EDP_HPD */ |
| 247 | PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), |
| 248 | /* E18 : DDPB_CTRLCLK ==> NC */ |
| 249 | PAD_CFG_NC(GPP_E18), |
| 250 | /* E19 : DDPB_CTRLDATA ==> NC */ |
| 251 | PAD_CFG_NC(GPP_E19), |
| 252 | /* E20 : DDPC_CTRLCLK ==> NC */ |
| 253 | PAD_CFG_NC(GPP_E20), |
| 254 | /* E21 : DDPC_CTRLDATA ==> NC */ |
| 255 | PAD_CFG_NC(GPP_E21), |
| 256 | /* E22 : DDPD_CTRLCLK ==> TRACKPAD_SHDN_L */ |
| 257 | PAD_CFG_GPO(GPP_E22, 1, DEEP), |
| 258 | /* E23 : DDPD_CTRLDATA ==> NC */ |
| 259 | PAD_CFG_NC(GPP_E23), |
| 260 | |
| 261 | /* F0 : I2S2_SCLK ==> BOOT_BEEP_BCLK */ |
| 262 | PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), |
| 263 | /* F1 : I2S2_SFRM ==> BOOT_BEEP_BUFFER_OE */ |
| 264 | PAD_CFG_GPO(GPP_F1, 1, DEEP), |
| 265 | /* F2 : I2S2_TXD ==> BOOT_BEEP_LRCLK */ |
| 266 | PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), |
| 267 | /* F3 : I2S2_RXD ==> NC */ |
| 268 | PAD_CFG_NC(GPP_F3), |
| 269 | /* F4 : I2C2_SDA ==> PCH_I2C2_TRACKPAD_1V8_SDA */ |
| 270 | PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), |
| 271 | /* F5 : I2C2_SCL ==> PCH_I2C2_TRACKPAD_1V8_SCL */ |
| 272 | PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), |
| 273 | /* F6 : I2C3_SDA ==> PCH_I2C3_CAMERA_1V8_SDA */ |
| 274 | PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), |
| 275 | /* F7 : I2C3_SCL ==> PCH_I2C3_CAMERA_1V8_SCL */ |
| 276 | PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), |
| 277 | /* F8 : I2C4_SDA ==> PCH_I2C4_AUDIO_1V8_SDA */ |
| 278 | PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), |
| 279 | /* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */ |
| 280 | PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), |
| 281 | /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */ |
| 282 | PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), |
| 283 | /* F11 : I2C5_SCL ==> SPKR_RST_L */ |
| 284 | PAD_CFG_GPO(GPP_F11, 1, RSMRST), |
| 285 | /* F12 : EMMC_CMD */ |
| 286 | PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), |
| 287 | /* F13 : EMMC_DATA0 */ |
| 288 | PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), |
| 289 | /* F14 : EMMC_DATA1 */ |
| 290 | PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), |
| 291 | /* F15 : EMMC_DATA2 */ |
| 292 | PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), |
| 293 | /* F16 : EMMC_DATA3 */ |
| 294 | PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), |
| 295 | /* F17 : EMMC_DATA4 */ |
| 296 | PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), |
| 297 | /* F18 : EMMC_DATA5 */ |
| 298 | PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), |
| 299 | /* F19 : EMMC_DATA6 */ |
| 300 | PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), |
| 301 | /* F20 : EMMC_DATA7 */ |
| 302 | PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), |
| 303 | /* F21 : EMMC_RCLK */ |
| 304 | PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), |
| 305 | /* F22 : EMMC_CLK */ |
| 306 | PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), |
| 307 | /* F23 : RSVD ==> NC */ |
| 308 | PAD_CFG_NC(GPP_F23), |
| 309 | |
| 310 | /* G0 : SD_CMD */ |
| 311 | PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), |
| 312 | /* G1 : SD_DATA0 */ |
| 313 | PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), |
| 314 | /* G2 : SD_DATA1 */ |
| 315 | PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), |
| 316 | /* G3 : SD_DATA2 */ |
| 317 | PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), |
| 318 | /* G4 : SD_DATA3 */ |
| 319 | PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), |
| 320 | /* G5 : SD_CD# */ |
| 321 | PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), |
| 322 | /* G6 : SD_CLK */ |
| 323 | PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), |
| 324 | /* G7 : SD_WP */ |
| 325 | PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), |
| 326 | |
| 327 | /* GPD0: BATLOW# ==> PCH_BATLOW_L */ |
| 328 | PAD_CFG_NF(GPD0, NONE, DEEP, NF1), |
| 329 | /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */ |
| 330 | PAD_CFG_NF(GPD1, NONE, DEEP, NF1), |
| 331 | /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ |
| 332 | PAD_CFG_NF(GPD2, NONE, DEEP, NF1), |
| 333 | /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ |
| 334 | PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), |
| 335 | /* GPD4: SLP_S3# ==> SLP_S3_L */ |
| 336 | PAD_CFG_NF(GPD4, NONE, DEEP, NF1), |
| 337 | /* GPD5: SLP_S4# ==> SLP_S4_L */ |
| 338 | PAD_CFG_NF(GPD5, NONE, DEEP, NF1), |
| 339 | /* GPD6: SLP_A# ==> NC */ |
| 340 | PAD_CFG_NC(GPD6), |
| 341 | /* GPD7: RSVD ==> NC */ |
| 342 | PAD_CFG_NC(GPD7), |
| 343 | /* GPD8: SUSCLK ==> PCH_SUSCLK */ |
| 344 | PAD_CFG_NF(GPD8, NONE, DEEP, NF1), |
| 345 | /* GPD9: SLP_WLAN# ==> NC */ |
| 346 | PAD_CFG_NC(GPD9), |
| 347 | /* GPD10: SLP_S5# ==> NC */ |
| 348 | PAD_CFG_NC(GPD10), |
| 349 | /* GPD11: LANPHYC ==> NC */ |
| 350 | PAD_CFG_NC(GPD11), |
| 351 | }; |
| 352 | |
| 353 | /* Early pad configuration in bootblock */ |
| 354 | static const struct pad_config early_gpio_table[] = { |
| 355 | /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ |
| 356 | PAD_CFG_GPO(GPP_B8, 0, RSMRST), |
| 357 | |
| 358 | /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ |
| 359 | PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), |
| 360 | /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ |
| 361 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), |
| 362 | /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ |
| 363 | PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), |
| 364 | /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ |
| 365 | PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), |
| 366 | |
| 367 | /* Ensure UART pins are in native mode for H1. */ |
| 368 | /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ |
| 369 | PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), |
| 370 | /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ |
| 371 | PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), |
| 372 | |
| 373 | /* C23 : UART2_CTS# ==> PCH_WP */ |
| 374 | PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), |
| 375 | |
| 376 | /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ |
| 377 | PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), |
| 378 | }; |
| 379 | |
| 380 | const struct pad_config *variant_gpio_table(size_t *num) |
| 381 | { |
| 382 | *num = ARRAY_SIZE(gpio_table); |
| 383 | return gpio_table; |
| 384 | } |
| 385 | |
| 386 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 387 | { |
| 388 | *num = ARRAY_SIZE(early_gpio_table); |
| 389 | return early_gpio_table; |
| 390 | } |