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Angel Pons182dbde2020-04-02 23:49:05 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Patrick Georgie72a8a32012-11-06 11:05:09 +01003
4#include <console/console.h>
5#include <device/device.h>
6#include <device/pci.h>
7#include <device/pci_ids.h>
8#include <device/pci_ops.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02009#include <device/mmio.h>
Patrick Georgie72a8a32012-11-06 11:05:09 +010010#include <delay.h>
Vladimir Serbinenko75c83872014-09-05 01:01:31 +020011#include <device/azalia_device.h>
Kyösti Mälkki12b121c2019-08-18 16:33:39 +030012#include "chip.h"
Patrick Georgie72a8a32012-11-06 11:05:09 +010013#include "i82801ix.h"
14
15#define HDA_ICII_REG 0x68
Andrew Wuae8d0692013-08-02 19:29:17 +080016#define HDA_ICII_BUSY (1 << 0)
17#define HDA_ICII_VALID (1 << 1)
Patrick Georgie72a8a32012-11-06 11:05:09 +010018
19typedef struct southbridge_intel_i82801ix_config config_t;
20
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080021static int set_bits(void *port, u32 mask, u32 val)
Patrick Georgie72a8a32012-11-06 11:05:09 +010022{
23 u32 reg32;
24 int count;
25
26 /* Write (val & mask) to port */
27 val &= mask;
28 reg32 = read32(port);
29 reg32 &= ~mask;
30 reg32 |= val;
31 write32(port, reg32);
32
33 /* Wait for readback of register to
34 * match what was just written to it
35 */
36 count = 50;
37 do {
38 /* Wait 1ms based on BKDG wait time */
39 mdelay(1);
40 reg32 = read32(port);
41 reg32 &= mask;
42 } while ((reg32 != val) && --count);
43
44 /* Timeout occurred */
45 if (!count)
46 return -1;
47 return 0;
48}
49
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080050static int codec_detect(u8 *base)
Patrick Georgie72a8a32012-11-06 11:05:09 +010051{
52 u32 reg32;
53
54 /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
55 if (set_bits(base + 0x08, 1, 0) == -1)
56 goto no_codec;
57
58 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
59 if (set_bits(base + 0x08, 1, 1) == -1)
60 goto no_codec;
61
62 /* Read in Codec location (BAR + 0xe)[2..0]*/
63 reg32 = read32(base + 0xe);
64 reg32 &= 0x0f;
65 if (!reg32)
66 goto no_codec;
67
68 return reg32;
69
70no_codec:
71 /* Codec Not found */
72 /* Put HDA back in reset (BAR + 0x8) [0] */
73 set_bits(base + 0x08, 1, 0);
74 printk(BIOS_DEBUG, "Azalia: No codec!\n");
75 return 0;
76}
77
Elyes HAOUASe414a4e2019-01-03 10:40:43 +010078static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb)
Patrick Georgie72a8a32012-11-06 11:05:09 +010079{
80 int idx=0;
81
82 while (idx < (cim_verb_data_size / sizeof(u32))) {
83 u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
84 if (cim_verb_data[idx] != viddid) {
85 idx += verb_size + 3; // skip verb + header
86 continue;
87 }
88 *verb = &cim_verb_data[idx+3];
89 return verb_size;
90 }
91
92 /* Not all codecs need to load another verb */
93 return 0;
94}
95
96/**
97 * Wait 50usec for the codec to indicate it is ready
98 * no response would imply that the codec is non-operative
99 */
100
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800101static int wait_for_ready(u8 *base)
Patrick Georgie72a8a32012-11-06 11:05:09 +0100102{
103 /* Use a 50 usec timeout - the Linux kernel uses the
104 * same duration */
105
106 int timeout = 50;
107
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200108 while (timeout--) {
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800109 u32 reg32 = read32(base + HDA_ICII_REG);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100110 if (!(reg32 & HDA_ICII_BUSY))
111 return 0;
112 udelay(1);
113 }
114
115 return -1;
116}
117
118/**
119 * Wait 50usec for the codec to indicate that it accepted
120 * the previous command. No response would imply that the code
121 * is non-operative
122 */
123
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800124static int wait_for_valid(u8 *base)
Patrick Georgie72a8a32012-11-06 11:05:09 +0100125{
126 u32 reg32;
127
128 /* Send the verb to the codec */
129 reg32 = read32(base + 0x68);
130 reg32 |= (1 << 0) | (1 << 1);
131 write32(base + 0x68, reg32);
132
133 /* Use a 50 usec timeout - the Linux kernel uses the
134 * same duration */
135
136 int timeout = 50;
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200137 while (timeout--) {
Patrick Georgie72a8a32012-11-06 11:05:09 +0100138 reg32 = read32(base + HDA_ICII_REG);
139 if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
140 HDA_ICII_VALID)
141 return 0;
142 udelay(1);
143 }
144
145 return -1;
146}
147
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800148static void codec_init(struct device *dev, u8 *base, int addr)
Patrick Georgie72a8a32012-11-06 11:05:09 +0100149{
150 u32 reg32;
151 const u32 *verb;
152 u32 verb_size;
153 int i;
154
155 printk(BIOS_DEBUG, "HD Audio: Initializing codec #%d\n", addr);
156
157 /* 1 */
158 if (wait_for_ready(base) == -1)
159 return;
160
161 reg32 = (addr << 28) | 0x000f0000;
162 write32(base + 0x60, reg32);
163
164 if (wait_for_valid(base) == -1)
165 return;
166
167 reg32 = read32(base + 0x64);
168
169 /* 2 */
170 printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
171 verb_size = find_verb(dev, reg32, &verb);
172
173 if (!verb_size) {
174 printk(BIOS_DEBUG, "Azalia: No verb!\n");
175 return;
176 }
177 printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
178
179 /* 3 */
180 for (i = 0; i < verb_size; i++) {
181 if (wait_for_ready(base) == -1)
182 return;
183
184 write32(base + 0x60, verb[i]);
185
186 if (wait_for_valid(base) == -1)
187 return;
188 }
189 printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
190}
191
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800192static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
Patrick Georgie72a8a32012-11-06 11:05:09 +0100193{
194 int i;
195 for (i = 2; i >= 0; i--) {
196 if (codec_mask & (1 << i))
197 codec_init(dev, base, i);
198 }
199
200 for (i = 0; i < pc_beep_verbs_size; i++) {
201 if (wait_for_ready(base) == -1)
202 return;
203
204 write32(base + 0x60, pc_beep_verbs[i]);
205
206 if (wait_for_valid(base) == -1)
207 return;
208 }
209}
210
211static void azalia_init(struct device *dev)
212{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800213 u8 *base;
Patrick Georgie72a8a32012-11-06 11:05:09 +0100214 struct resource *res;
215 u32 codec_mask;
216 u8 reg8;
217 u32 reg32;
218
Patrick Georgie72a8a32012-11-06 11:05:09 +0100219 // ESD
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300220 reg32 = pci_read_config32(dev, 0x134);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100221 reg32 &= 0xff00ffff;
222 reg32 |= (2 << 16);
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300223 pci_write_config32(dev, 0x134, reg32);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100224
225 // Link1 description
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300226 reg32 = pci_read_config32(dev, 0x140);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100227 reg32 &= 0xff00ffff;
228 reg32 |= (2 << 16);
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300229 pci_write_config32(dev, 0x140, reg32);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100230
231 // Port VC0 Resource Control Register
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300232 reg32 = pci_read_config32(dev, 0x114);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100233 reg32 &= 0xffffff00;
234 reg32 |= 1;
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300235 pci_write_config32(dev, 0x114, reg32);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100236
237 // VCi traffic class
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300238 reg8 = pci_read_config8(dev, 0x44);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100239 reg8 |= (7 << 0); // TC7
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300240 pci_write_config8(dev, 0x44, reg8);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100241
242 // VCi Resource Control
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300243 reg32 = pci_read_config32(dev, 0x120);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100244 reg32 |= (1 << 31);
245 reg32 |= (1 << 24); // VCi ID
246 reg32 |= (0x80 << 0); // VCi map
Kyösti Mälkki9b143e12013-07-26 08:35:09 +0300247 pci_write_config32(dev, 0x120, reg32);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100248
249 /* Set Bus Master */
Elyes HAOUASb9d2e222020-04-28 10:25:12 +0200250 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100251
252 reg8 = pci_read_config8(dev, 0x4d); // Docking Status
253 reg8 &= ~(1 << 7); // Docking not supported
254 pci_write_config8(dev, 0x4d, reg8);
255
256 /* Lock some R/WO bits by writing their current value. */
257 reg32 = pci_read_config32(dev, 0x74);
258 pci_write_config32(dev, 0x74, reg32);
259
260 res = find_resource(dev, 0x10);
261 if (!res)
262 return;
263
264 // NOTE this will break as soon as the Azalia get's a bar above
265 // 4G. Is there anything we can do about it?
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800266 base = res2mmio(res, 0, 0);
Patrick Rudolph4af2add2018-11-26 15:56:11 +0100267 printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
Patrick Georgie72a8a32012-11-06 11:05:09 +0100268 codec_mask = codec_detect(base);
269
270 if (codec_mask) {
271 printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
272 codecs_init(dev, base, codec_mask);
273 }
274}
275
Patrick Georgie72a8a32012-11-06 11:05:09 +0100276static struct pci_operations azalia_pci_ops = {
Subrata Banik4a0f0712019-03-20 14:29:47 +0530277 .set_subsystem = pci_dev_set_subsystem,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100278};
279
280static struct device_operations azalia_ops = {
281 .read_resources = pci_dev_read_resources,
282 .set_resources = pci_dev_set_resources,
283 .enable_resources = pci_dev_enable_resources,
284 .init = azalia_init,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100285 .ops_pci = &azalia_pci_ops,
286};
287
288/* ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M */
289static const struct pci_driver i82801ix_azalia __pci_driver = {
290 .ops = &azalia_ops,
291 .vendor = PCI_VENDOR_ID_INTEL,
Felix Singer7f8b0cd2019-11-10 11:04:08 +0100292 .device = PCI_DEVICE_ID_INTEL_82801IB_HD_AUDIO,
Patrick Georgie72a8a32012-11-06 11:05:09 +0100293};