| Sheng-Liang Pan | b9c2345 | 2021-05-31 19:41:02 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <baseboard/variants.h> |
| 4 | |
| 5 | static const struct mb_cfg board_memcfg = { |
| 6 | .type = MEM_TYPE_LP4X, |
| 7 | |
| 8 | /* DQ byte map */ |
| 9 | .lp4x_dq_map = { |
| 10 | .ddr0 = { |
| 11 | .dq0 = { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ |
| 12 | .dq1 = { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ |
| 13 | }, |
| 14 | .ddr1 = { |
| 15 | .dq0 = { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ |
| 16 | .dq1 = { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ |
| 17 | }, |
| 18 | .ddr2 = { |
| 19 | .dq0 = { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ |
| 20 | .dq1 = { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ |
| 21 | }, |
| 22 | .ddr3 = { |
| 23 | .dq0 = { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ |
| 24 | .dq1 = { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ |
| 25 | }, |
| 26 | .ddr4 = { |
| 27 | .dq0 = { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ |
| 28 | .dq1 = { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ |
| 29 | }, |
| 30 | .ddr5 = { |
| 31 | .dq0 = { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ |
| 32 | .dq1 = { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ |
| 33 | }, |
| 34 | .ddr6 = { |
| 35 | .dq0 = { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ |
| 36 | .dq1 = { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ |
| 37 | }, |
| 38 | .ddr7 = { |
| 39 | .dq0 = { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ |
| 40 | .dq1 = { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ |
| 41 | }, |
| 42 | }, |
| 43 | |
| 44 | /* DQS CPU<>DRAM map */ |
| 45 | .lp4x_dqs_map = { |
| 46 | .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ |
| 47 | .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ |
| 48 | .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ |
| 49 | .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ |
| 50 | .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ |
| 51 | .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR5_DQS[1:0] */ |
| 52 | .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ |
| 53 | .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ |
| 54 | }, |
| 55 | |
| 56 | .ect = true, /* Enable Early Command Training */ |
| 57 | }; |
| 58 | |
| 59 | const struct mb_cfg *variant_memory_params(void) |
| 60 | { |
| 61 | return &board_memcfg; |
| 62 | } |