Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | #include <assert.h> |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <fsp/ppi/mp_service_ppi.h> |
| 7 | #include <fsp/util.h> |
| 8 | #include <intelblocks/lpss.h> |
| 9 | #include <intelblocks/mp_init.h> |
| 10 | #include <intelblocks/xdci.h> |
| 11 | #include <intelpch/lockdown.h> |
| 12 | #include <soc/intel/common/vbt.h> |
| 13 | #include <soc/pci_devs.h> |
| 14 | #include <soc/ramstage.h> |
| 15 | #include <soc/soc_chip.h> |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 16 | #include <string.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 17 | |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 18 | /* SATA DEVSLP idle timeout default values */ |
| 19 | #define DEF_DMVAL 15 |
| 20 | #define DEF_DITOVAL_MS 625 |
| 21 | |
| 22 | /* Native function controls pads termination */ |
| 23 | #define GPIO_TERM_NATIVE 0x1F |
| 24 | |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 25 | /* |
| 26 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 27 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 28 | * In order to ensure that mainboard setting does not disable L1 substates |
| 29 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 30 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 31 | * value is set in fsp_params. |
| 32 | * 0: Use FSP UPD default |
| 33 | * 1: Disable L1 substates |
| 34 | * 2: Use L1.1 |
| 35 | * 3: Use L1.2 (FSP UPD default) |
| 36 | */ |
| 37 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 38 | { |
| 39 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 40 | ctl = L1_SS_L1_2; |
| 41 | return ctl - 1; |
| 42 | } |
| 43 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 44 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 45 | { |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 46 | const struct soc_intel_elkhartlake_config *config = config_of_soc(); |
| 47 | |
| 48 | /* LPSS controllers configuration */ |
| 49 | |
| 50 | /* I2C */ |
| 51 | _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >= |
| 52 | ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!"); |
| 53 | memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, |
| 54 | sizeof(config->SerialIoI2cMode)); |
| 55 | |
| 56 | _Static_assert(ARRAY_SIZE(params->PchSerialIoI2cPadsTermination) >= |
| 57 | ARRAY_SIZE(config->SerialIoI2cPadsTermination), |
| 58 | "copy buffer overflow!"); |
| 59 | memcpy(params->PchSerialIoI2cPadsTermination, config->SerialIoI2cPadsTermination, |
| 60 | sizeof(config->SerialIoI2cPadsTermination)); |
| 61 | |
| 62 | params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09; //GPIO native mode for GPP_H9 |
| 63 | params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08; //GPIO native mode for GPP_H8 |
| 64 | |
| 65 | /* GSPI */ |
| 66 | _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >= |
| 67 | ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!"); |
| 68 | memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode, |
| 69 | sizeof(config->SerialIoGSpiMode)); |
| 70 | |
| 71 | _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsEnable) >= |
| 72 | ARRAY_SIZE(config->SerialIoGSpiCsEnable), "copy buffer overflow!"); |
| 73 | memcpy(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable, |
| 74 | sizeof(config->SerialIoGSpiCsEnable)); |
| 75 | |
| 76 | _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >= |
| 77 | ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!"); |
| 78 | memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode, |
| 79 | sizeof(config->SerialIoGSpiCsMode)); |
| 80 | |
| 81 | _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >= |
| 82 | ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!"); |
| 83 | memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState, |
| 84 | sizeof(config->SerialIoGSpiCsState)); |
| 85 | |
| 86 | params->SerialIoSpiCsPolarity[2] = 0; |
| 87 | |
| 88 | /* UART */ |
| 89 | _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >= |
| 90 | ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!"); |
| 91 | memcpy(params->SerialIoUartMode, config->SerialIoUartMode, |
| 92 | sizeof(config->SerialIoUartMode)); |
| 93 | |
| 94 | _Static_assert(ARRAY_SIZE(params->SerialIoUartDmaEnable) >= |
| 95 | ARRAY_SIZE(config->SerialIoUartDmaEnable), "copy buffer overflow!"); |
| 96 | memcpy(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable, |
| 97 | sizeof(config->SerialIoUartDmaEnable)); |
| 98 | |
| 99 | params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F; //GPIO native mode for GPP_T15 |
| 100 | params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E; //GPIO native mode for GPP_T14 |
| 101 | params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C; //GPIO native mode for GPP_T12 |
| 102 | params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D; //GPIO native mode for GPP_T13 |
| 103 | |
| 104 | /* Provide correct UART number for FSP debug logs */ |
| 105 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | /* UPD parameters to be initialized before SiliconInit */ |
| 109 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 110 | { |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 111 | unsigned int i; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 112 | struct device *dev; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 113 | FSP_S_CONFIG *params = &supd->FspsConfig; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 114 | struct soc_intel_elkhartlake_config *config = config_of_soc(); |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 115 | |
| 116 | /* Parse device tree and fill in FSP UPDs */ |
| 117 | parse_devicetree(params); |
| 118 | |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 119 | /* Load VBT before devicetree-specific config. */ |
| 120 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 121 | |
| 122 | /* Check if IGD is present and fill Graphics init param accordingly */ |
| 123 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 124 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); |
| 125 | |
| 126 | /* Display config */ |
| 127 | params->DdiPortAHpd = config->DdiPortAHpd; |
| 128 | params->DdiPortADdc = config->DdiPortADdc; |
| 129 | params->DdiPortCHpd = config->DdiPortCHpd; |
| 130 | params->DdiPortCDdc = config->DdiPortCDdc; |
| 131 | |
| 132 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 133 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 134 | params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 135 | |
| 136 | /* Chipset Lockdown */ |
| 137 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
| 138 | params->PchLockDownGlobalSmi = 0; |
| 139 | params->PchLockDownBiosLock = 0; |
| 140 | params->PchLockDownBiosInterface = 0; |
| 141 | params->PchWriteProtectionEnable[0] = 0; |
| 142 | params->PchUnlockGpioPads = 1; |
| 143 | params->RtcMemoryLock = 0; |
| 144 | } else { |
| 145 | params->PchLockDownGlobalSmi = 1; |
| 146 | params->PchLockDownBiosLock = 1; |
| 147 | params->PchLockDownBiosInterface = 1; |
| 148 | params->PchWriteProtectionEnable[0] = 1; |
| 149 | params->PchUnlockGpioPads = 0; |
| 150 | params->RtcMemoryLock = 1; |
| 151 | } |
| 152 | |
| 153 | /* Disable PAVP */ |
| 154 | params->PavpEnable = 0; |
| 155 | |
| 156 | /* Legacy 8254 timer support */ |
| 157 | params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); |
| 158 | params->Enable8254ClockGatingOnS3 = 1; |
| 159 | |
| 160 | /* PCH Master Gating Control */ |
| 161 | params->PchPostMasterClockGating = 1; |
| 162 | params->PchPostMasterPowerGating = 1; |
| 163 | |
| 164 | /* HECI */ |
| 165 | params->Heci3Enabled = config->Heci3Enable; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 166 | |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 167 | /* USB configuration */ |
| 168 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 169 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 170 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 171 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 172 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 173 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 174 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].enable ? |
| 175 | config->usb2_ports[i].ocpin : 0xff; |
| 176 | } |
| 177 | |
| 178 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 179 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 180 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].enable ? |
| 181 | config->usb3_ports[i].ocpin : 0xff; |
| 182 | if (config->usb3_ports[i].tx_de_emp) { |
| 183 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 184 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 185 | } |
| 186 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 187 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 188 | params->Usb3HsioTxDownscaleAmp[i] = |
| 189 | config->usb3_ports[i].tx_downscale_amp; |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | params->UsbClockGatingEnable = 1; |
| 194 | params->UsbPowerGatingEnable = 1; |
| 195 | |
| 196 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
| 197 | dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); |
| 198 | if (dev) { |
| 199 | if (!xdci_can_enable()) |
| 200 | dev->enabled = 0; |
| 201 | |
| 202 | params->XdciEnable = dev->enabled; |
| 203 | } else { |
| 204 | params->XdciEnable = 0; |
| 205 | } |
| 206 | |
| 207 | /* PCIe root ports config */ |
| 208 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
| 209 | params->PcieRpClkReqDetect[i] = |
| 210 | !config->PcieRpClkReqDetectDisable[i]; |
| 211 | params->PcieRpL1Substates[i] = |
| 212 | get_l1_substate_control(config->PcieRpL1Substates[i]); |
| 213 | params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i]; |
| 214 | params->PcieRpAdvancedErrorReporting[i] = |
| 215 | !config->PcieRpAdvancedErrorReportingDisable[i]; |
| 216 | params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; |
| 217 | params->PciePtm[i] = config->PciePtm[i]; |
| 218 | params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003; |
| 219 | params->PcieRpLtrMaxSnoopLatency[i] = 0x1003; |
| 220 | /* Virtual Channel 1 to Traffic Class mapping */ |
| 221 | params->PcieRpVc1TcMap[i] = 0x60; |
| 222 | } |
| 223 | |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 224 | /* SATA config */ |
| 225 | dev = pcidev_path_on_root(PCH_DEVFN_SATA); |
| 226 | params->SataEnable = is_dev_enabled(dev); |
| 227 | if (params->SataEnable) { |
| 228 | params->SataMode = config->SataMode; |
| 229 | params->SataSalpSupport = config->SataSalpSupport; |
| 230 | params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
| 231 | |
| 232 | for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) { |
| 233 | params->SataPortsEnable[i] = config->SataPortsEnable[i]; |
| 234 | params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i]; |
| 235 | if (config->SataPortsEnableDitoConfig[i]) { |
| 236 | params->SataPortsDmVal[i] = |
| 237 | config->SataPortsDmVal[i] ? : DEF_DMVAL; |
| 238 | params->SataPortsDitoVal[i] = |
| 239 | config->SataPortsDitoVal[i] ? : DEF_DITOVAL_MS; |
| 240 | } |
| 241 | } |
| 242 | } |
| 243 | |
| 244 | /* SDCard config */ |
| 245 | dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); |
| 246 | params->ScsSdCardEnabled = is_dev_enabled(dev); |
| 247 | if (params->ScsSdCardEnabled) { |
| 248 | params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; |
| 249 | params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE; |
| 250 | params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE; |
| 251 | params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE; |
| 252 | params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE; |
| 253 | params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE; |
| 254 | } |
| 255 | |
| 256 | /* eMMC config */ |
| 257 | dev = pcidev_path_on_root(PCH_DEVFN_EMMC); |
| 258 | params->ScsEmmcEnabled = is_dev_enabled(dev); |
| 259 | if (params->ScsEmmcEnabled) { |
| 260 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 261 | params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled; |
| 262 | } |
| 263 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 264 | /* Override/Fill FSP Silicon Param for mainboard */ |
| 265 | mainboard_silicon_init_params(params); |
| 266 | } |
| 267 | |
| 268 | /* Mainboard GPIO Configuration */ |
| 269 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 270 | { |
| 271 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 272 | } |