| Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Aamir Bohra | 237a93c | 2017-04-06 11:10:35 +0530 | [diff] [blame] | 2 | |
| 3 | #ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H |
| 4 | #define SOC_INTEL_COMMON_BLOCK_LPSS_H |
| 5 | |
| Aamir Bohra | cc8e992 | 2019-07-12 14:34:02 +0530 | [diff] [blame] | 6 | #include <device/device.h> |
| Aamir Bohra | 237a93c | 2017-04-06 11:10:35 +0530 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
| Aamir Bohra | cc8e992 | 2019-07-12 14:34:02 +0530 | [diff] [blame] | 9 | /* D0 and D3 enable config */ |
| 10 | enum lpss_pwr_state { |
| 11 | STATE_D0 = 0, |
| 12 | STATE_D3 = 3 |
| 13 | }; |
| 14 | |
| Aamir Bohra | 237a93c | 2017-04-06 11:10:35 +0530 | [diff] [blame] | 15 | /* Gets controller out of reset */ |
| 16 | void lpss_reset_release(uintptr_t base); |
| 17 | |
| 18 | /* |
| Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 19 | * Update clock divider parameters. Clock frequency is dependent on source |
| 20 | * clock frequency of each IP block. Resulting clock will be src_freq * (M / N). |
| Aamir Bohra | 237a93c | 2017-04-06 11:10:35 +0530 | [diff] [blame] | 21 | */ |
| 22 | void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); |
| 23 | |
| Furquan Shaikh | 3b90b5f | 2017-08-04 16:04:46 -0700 | [diff] [blame] | 24 | /* Check if controller is in reset. */ |
| 25 | bool lpss_is_controller_in_reset(uintptr_t base); |
| 26 | |
| Aamir Bohra | cc8e992 | 2019-07-12 14:34:02 +0530 | [diff] [blame] | 27 | /* Set controller power state to D0 or D3*/ |
| Furquan Shaikh | fb29ca0 | 2021-01-02 00:03:00 -0800 | [diff] [blame] | 28 | void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state); |
| Aamir Bohra | cc8e992 | 2019-07-12 14:34:02 +0530 | [diff] [blame] | 29 | |
| Aamir Bohra | 237a93c | 2017-04-06 11:10:35 +0530 | [diff] [blame] | 30 | #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ |