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review.coreboot.org / coreboot / b95ef282ff785f63ce2a74ff0140072856893687 / . / src / southbridge / intel / bd82x6x / common.c
blob: 7163d3edc7bdf300cf671fa045df28c4ca0a63a5 [file] [log] [blame]
Angel Ponsb4492392021-01-06 01:56:14 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#define __SIMPLE_DEVICE__
4
5#include <console/console.h>
6#include <delay.h>
7#include <device/pci.h>
8#include <device/pci_def.h>
9#include <device/pci_ids.h>
10#include <device/pci_ops.h>
11#include <stdint.h>
12
13#include "pch.h"
14
15int pch_silicon_revision(void)
16{
17 static int pch_revision_id = -1;
18
19 if (pch_revision_id < 0)
20 pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
21
22 return pch_revision_id;
23}
24
25int pch_silicon_type(void)
26{
27 static int pch_type = -1;
28
29 if (pch_type < 0)
30 pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
31
32 return pch_type;
33}
34
Patrick Rudolphb95ef282023-11-04 11:08:25 +0100[diff] [blame^]35bool pch_is_mobile(void)
36{
37 const u16 devids[] = {
38 PCI_DID_INTEL_6_SERIES_MOBILE_SFF, PCI_DID_INTEL_6_SERIES_MOBILE,
39 PCI_DID_INTEL_6_SERIES_UM67, PCI_DID_INTEL_6_SERIES_HM65,
40 PCI_DID_INTEL_6_SERIES_HM67, PCI_DID_INTEL_6_SERIES_QS67,
41 PCI_DID_INTEL_6_SERIES_QM67,
42 PCI_DID_INTEL_7_SERIES_MOBILE, PCI_DID_INTEL_7_SERIES_MOBILE_SFF,
43 PCI_DID_INTEL_7_SERIES_QM77, PCI_DID_INTEL_7_SERIES_QS77,
44 PCI_DID_INTEL_7_SERIES_HM77, PCI_DID_INTEL_7_SERIES_UM77,
45 PCI_DID_INTEL_7_SERIES_HM76, PCI_DID_INTEL_7_SERIES_HM75,
46 PCI_DID_INTEL_7_SERIES_HM70, PCI_DID_INTEL_7_SERIES_NM70
47 };
48 u16 devid = pci_s_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID);
49
50 for (size_t i = 0; i < ARRAY_SIZE(devids); i++)
51 if (devid == devids[i])
52 return true;
53 return false;
54}
55
Angel Ponsb4492392021-01-06 01:56:14 +0100[diff] [blame]56int pch_silicon_supported(int type, int rev)
57{
58 int cur_type = pch_silicon_type();
59 int cur_rev = pch_silicon_revision();
60
61 switch (type) {
62 case PCH_TYPE_CPT:
63 /* CougarPoint minimum revision */
64 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
65 return 1;
66 /* PantherPoint any revision */
67 if (cur_type == PCH_TYPE_PPT)
68 return 1;
69 break;
70
71 case PCH_TYPE_PPT:
72 /* PantherPoint minimum revision */
73 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
74 return 1;
75 break;
76 }
77
78 return 0;
79}
80
81#define IOBP_RETRY 1000
82static inline int iobp_poll(void)
83{
84 unsigned int try = IOBP_RETRY;
85 u32 data;
86
87 while (try--) {
88 data = RCBA32(IOBPS);
89 if ((data & 1) == 0)
90 return 1;
91 udelay(10);
92 }
93
94 printk(BIOS_ERR, "IOBP timeout\n");
95 return 0;
96}
97
98void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
99{
100 u32 data;
101
102 /* Set the address */
103 RCBA32(IOBPIRI) = address;
104
105 /* READ OPCODE */
106 if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
107 RCBA32(IOBPS) = IOBPS_RW_BX;
108 else
109 RCBA32(IOBPS) = IOBPS_READ_AX;
110 if (!iobp_poll())
111 return;
112
113 /* Read IOBP data */
114 data = RCBA32(IOBPD);
115 if (!iobp_poll())
116 return;
117
118 /* Check for successful transaction */
119 if ((RCBA32(IOBPS) & 0x6) != 0) {
120 printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
121 return;
122 }
123
124 /* Update the data */
125 data &= andvalue;
126 data |= orvalue;
127
128 /* WRITE OPCODE */
129 if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
130 RCBA32(IOBPS) = IOBPS_RW_BX;
131 else
132 RCBA32(IOBPS) = IOBPS_WRITE_AX;
133 if (!iobp_poll())
134 return;
135
136 /* Write IOBP data */
137 RCBA32(IOBPD) = data;
138 if (!iobp_poll())
139 return;
140}