Yunlong Jia | 8cc0faa | 2023-04-26 08:53:48 +0000 | [diff] [blame] | 1 | chip soc/intel/alderlake |
| 2 | |
Simon Yang | b940728 | 2023-07-03 22:00:09 +0800 | [diff] [blame^] | 3 | # EMMC Tx CMD Delay |
| 4 | # Refer to EDS-Vol2-42.3.7. |
| 5 | # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. |
| 6 | # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. |
| 7 | register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" |
| 8 | |
| 9 | # EMMC TX DATA Delay 1 |
| 10 | # Refer to EDS-Vol2-42.3.8. |
| 11 | # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. |
| 12 | # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. |
| 13 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" |
| 14 | |
| 15 | # EMMC TX DATA Delay 2 |
| 16 | # Refer to EDS-Vol2-42.3.9. |
| 17 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. |
| 18 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 19 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. |
| 20 | # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. |
| 21 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" |
| 22 | |
| 23 | # EMMC RX CMD/DATA Delay 1 |
| 24 | # Refer to EDS-Vol2-42.3.10. |
| 25 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. |
| 26 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 27 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. |
| 28 | # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. |
| 29 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D1B" |
| 30 | |
| 31 | # EMMC RX CMD/DATA Delay 2 |
| 32 | # Refer to EDS-Vol2-42.3.12. |
| 33 | # [17:16] stands for Rx Clock before Output Buffer, |
| 34 | # 00: Rx clock after output buffer, |
| 35 | # 01: Rx clock before output buffer, |
| 36 | # 10: Automatic selection based on working mode. |
| 37 | # 11: Reserved |
| 38 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. |
| 39 | # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. |
| 40 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004c" |
| 41 | |
| 42 | # EMMC Rx Strobe Delay |
| 43 | # Refer to EDS-Vol2-42.3.11. |
| 44 | # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. |
| 45 | # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. |
| 46 | register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" |
| 47 | |
Yunlong Jia | 8cc0faa | 2023-04-26 08:53:48 +0000 | [diff] [blame] | 48 | device domain 0 on |
| 49 | end |
| 50 | |
| 51 | end |