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review.coreboot.org / coreboot / b907d321a5d0957f5cbb03d8f9c8d0ff0c23523b / . / src / mainboard / via / epia-n / mptable.c
blob: 9ffa2b1765758108a0136ec0c259a5dc21800335 [file] [log] [blame]
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]1/* generated by MPTable, version 2.0.15*/
2/* as modified by RGM for coreboot */
3#include <console/console.h>
4#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]5#include <arch/ioapic.h>
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]6#include <device/pci.h>
7#include <string.h>
8#include <stdint.h>
9
Myles Watson08e0fb82010-03-22 16:33:25 +0000[diff] [blame]10static void *smp_write_config_table(void *v)
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]11{
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]12 struct mp_config_table *mc;
Patrick Georgi20979582010-09-24 18:42:56 +0000[diff] [blame]13 int isa_bus;
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]14
15 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]16
Uwe Hermann55dc2232010-10-25 15:32:07 +0000[diff] [blame]17 mptable_init(mc, "EPIA-N ", LAPIC_ADDR);
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]18
19 smp_write_processors(mc);
Patrick Georgi20979582010-09-24 18:42:56 +0000[diff] [blame]20 mptable_write_buses(mc, NULL, &isa_bus);
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]21
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]22/*I/O APICs: APIC ID Version State Address*/
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]23 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]24 {
25 device_t dev;
26 struct resource *res;
27 dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
28 if (dev) {
29 res = find_resource(dev, PCI_BASE_ADDRESS_0);
30 if (res) {
31 smp_write_ioapic(mc, 3, 0x20, res->base);
32 }
33 }
34 dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
35 if (dev) {
36 res = find_resource(dev, PCI_BASE_ADDRESS_0);
37 if (res) {
38 smp_write_ioapic(mc, 4, 0x20, res->base);
39 }
40 }
41 dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
42 if (dev) {
43 res = find_resource(dev, PCI_BASE_ADDRESS_0);
44 if (res) {
45 smp_write_ioapic(mc, 5, 0x20, res->base);
46 }
47 }
48 dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
49 if (dev) {
50 res = find_resource(dev, PCI_BASE_ADDRESS_0);
51 if (res) {
52 smp_write_ioapic(mc, 8, 0x20, res->base);
53 }
54 }
55 }
Patrick Georgi20979582010-09-24 18:42:56 +0000[diff] [blame]56 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
Patrick Georgic5b87c82010-05-20 15:28:19 +0000[diff] [blame]57
58/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
59 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
61 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
62 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16);
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14);
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]68/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
Tobias Diedrichb907d322010-10-26 22:40:16 +0000[diff] [blame^]69 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
70 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]71 /* There is no extension information... */
72
73 /* Compute the checksums */
74 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
75 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]76 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
Jon Harrison9c2e7382009-08-18 15:12:13 +0000[diff] [blame]77 mc, smp_next_mpe_entry(mc));
78 return smp_next_mpe_entry(mc);
79}
80
81unsigned long write_smp_table(unsigned long addr)
82{
83 void *v;
84 v = smp_write_floating_table(addr);
85 return (unsigned long)smp_write_config_table(v);
86}