Blame - src/mainboard/tyan/s2880/mptable.c - coreboot

2003-07-21 20:13:45 +0000

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#include <console/console.h>

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#include <arch/smp/mpspec.h>

Uwe Hermann

74d1a6e

2010-10-12 17:34:08 +0000

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#include <arch/ioapic.h>

Eric Biederman

2003-07-21 20:13:45 +0000

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#include <device/pci.h>

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#include <string.h>

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#include <stdint.h>

arch import user (historical)

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#if CONFIG_LOGICAL_CPUS==1

Stefan Reinauer

9a16e3e

2010-03-29 14:45:36 +0000

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#include <cpu/amd/multicore.h>

arch import user (historical)

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#endif

Eric Biederman

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Yinghai Lu

2005-07-08 02:49:49 +0000

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static unsigned node_link_to_bus(unsigned node, unsigned link)

{

device_t dev;

unsigned reg;

dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));

if (!dev) {

return 0;

}

for(reg = 0xE0; reg < 0xF0; reg += 0x04) {

uint32_t config_map;

unsigned dst_node;

unsigned dst_link;

unsigned bus_base;

config_map = pci_read_config32(dev, reg);

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if ((config_map & 3) != 3) {

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continue;

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}

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dst_node = (config_map >> 4) & 7;

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dst_link = (config_map >> 8) & 3;

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bus_base = (config_map >> 16) & 0xff;

Stefan Reinauer

2010-04-27 06:56:47 +0000

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#if 0

Stefan Reinauer

2010-03-22 11:42:32 +0000

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printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",

Yinghai Lu

2005-07-08 02:49:49 +0000

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dst_node, dst_link, bus_base,

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reg, config_map);

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#endif

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if ((dst_node == node) && (dst_link == link))

{

return bus_base;

}

}

return 0;

}

Myles Watson

2010-03-22 16:33:25 +0000

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static void *smp_write_config_table(void *v)

Eric Biederman

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{

Eric Biederman

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struct mp_config_table *mc;

Patrick Georgi

2097958

2010-09-24 18:42:56 +0000

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int bus_isa;

Yinghai Lu

2005-07-08 02:49:49 +0000

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unsigned char bus_chain_0;

Ronald G. Minnich

2003-12-02 03:58:19 +0000

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unsigned char bus_8131_1;

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unsigned char bus_8131_2;

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unsigned char bus_8111_1;

arch import user (historical)

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unsigned apicid_base;

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unsigned apicid_8111;

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unsigned apicid_8131_1;

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unsigned apicid_8131_2;

Stefan Reinauer

2010-04-27 06:56:47 +0000

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Eric Biederman

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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);

Eric Biederman

2003-07-21 20:13:45 +0000

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Uwe Hermann

55dc223

2010-10-25 15:32:07 +0000

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mptable_init(mc, "S2880 ", LAPIC_ADDR);

Eric Biederman

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Yinghai Lu

2004-10-20 05:07:16 +0000

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smp_write_processors(mc);

Eric Biederman

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Ronald G. Minnich

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{

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device_t dev;

Yinghai Lu

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/* HT chain 0 */

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bus_chain_0 = node_link_to_bus(0, 0);

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if (bus_chain_0 == 0) {

Stefan Reinauer

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printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");

Yinghai Lu

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bus_chain_0 = 1;

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}

Stefan Reinauer

2010-04-27 06:56:47 +0000

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Ronald G. Minnich

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/* 8111 */

Yinghai Lu

2005-07-08 02:49:49 +0000

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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));

Ronald G. Minnich

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if (dev) {

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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);

Stefan Reinauer

2010-04-27 06:56:47 +0000

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}

Ronald G. Minnich

2003-12-02 03:58:19 +0000

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else {

Stefan Reinauer

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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");

Eric Biederman

2003-07-21 20:13:45 +0000

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Ronald G. Minnich

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bus_8111_1 = 4;

Ronald G. Minnich

2003-12-02 03:58:19 +0000

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}

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/* 8131-1 */

Yinghai Lu

2005-07-08 02:49:49 +0000

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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));

Ronald G. Minnich

2003-12-02 03:58:19 +0000

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if (dev) {

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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);

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}

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else {

Stefan Reinauer

2010-03-22 11:42:32 +0000

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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");

Ronald G. Minnich

2003-12-02 03:58:19 +0000

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bus_8131_1 = 2;

}

/* 8131-2 */

Yinghai Lu

2005-07-08 02:49:49 +0000

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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));

Ronald G. Minnich

2003-12-02 03:58:19 +0000

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if (dev) {

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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);

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}

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else {

Stefan Reinauer

2010-03-22 11:42:32 +0000

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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");

Ronald G. Minnich

2003-12-02 03:58:19 +0000

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bus_8131_2 = 3;

}

}

/*Bus: Bus ID Type*/

Patrick Georgi

2097958

2010-09-24 18:42:56 +0000

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mptable_write_buses(mc, NULL, &bus_isa);

Stefan Reinauer

2010-04-27 06:56:47 +0000

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Eric Biederman

2003-07-21 20:13:45 +0000

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/*I/O APICs: APIC ID Version State Address*/

arch import user (historical)

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#if CONFIG_LOGICAL_CPUS==1

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apicid_base = get_apicid_base(3);

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#else

Stefan Reinauer

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apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

arch import user (historical)

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#endif

Stefan Reinauer

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apicid_8111 = apicid_base+0;

arch import user (historical)

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apicid_8131_1 = apicid_base+1;

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apicid_8131_2 = apicid_base+2;

Uwe Hermann

74d1a6e

2010-10-12 17:34:08 +0000

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smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);

Eric Biederman

2003-07-21 20:13:45 +0000

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{

Yinghai Lu

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device_t dev;

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struct resource *res;

Yinghai Lu

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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));

Eric Biederman

2003-07-21 20:13:45 +0000

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if (dev) {

Yinghai Lu

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res = find_resource(dev, PCI_BASE_ADDRESS_0);

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if (res) {

arch import user (historical)

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smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);

Yinghai Lu

2004-10-20 05:07:16 +0000

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}

Eric Biederman

2003-07-21 20:13:45 +0000

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}

Yinghai Lu

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dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));

Eric Biederman

2003-07-21 20:13:45 +0000

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if (dev) {

Yinghai Lu

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res = find_resource(dev, PCI_BASE_ADDRESS_0);

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if (res) {

arch import user (historical)

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smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);

Yinghai Lu

2004-10-20 05:07:16 +0000

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}

Eric Biederman

2003-07-21 20:13:45 +0000

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}

Yinghai Lu

2004-10-20 05:07:16 +0000

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Eric Biederman

2003-07-21 20:13:45 +0000

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}

Stefan Reinauer

2010-04-27 06:56:47 +0000

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Patrick Georgi

c5b87c8

2010-05-20 15:28:19 +0000

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mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);

Stefan Reinauer

2010-04-27 06:56:47 +0000

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Patrick Georgi

c5b87c8

2010-05-20 15:28:19 +0000

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/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */

Yinghai Lu

2005-07-08 02:49:49 +0000

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);

Ronald G. Minnich

2003-12-02 03:58:19 +0000

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Ronald G. Minnich

2003-08-04 22:13:57 +0000

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//On Board AMD USB

arch import user (historical)

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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//On Board ATI Display Adapter

arch import user (historical)

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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//Slot 5 PCI 32

arch import user (historical)

2005-07-06 17:15:30 +0000

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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//On Board Promise Serial ATA

arch import user (historical)

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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//Slot 3 PCIX 100/66

arch import user (historical)

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x3);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x0);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);//

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);//

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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Stefan Reinauer

2010-04-27 06:56:47 +0000

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//Slot 4 PCIX 100/66

arch import user (historical)

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, apicid_8131_1, 0x2);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, apicid_8131_1, 0x3);//

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, apicid_8131_1, 0x0);//

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|3, apicid_8131_1, 0x1);//

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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//On Board NIC and LSI scsi

arch import user (historical)

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x0);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x1);

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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//Slot 1 PCI-X 133/100/66

arch import user (historical)

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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//Slot 2 PCI-X 133/100/66

arch import user (historical)

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x1);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x2);

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, apicid_8131_2, 0x3);//

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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);//

Ronald G. Minnich

2003-08-04 22:13:57 +0000

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192

Eric Biederman

2003-07-21 20:13:45 +0000

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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/

Tobias Diedrich

b907d32

2010-10-26 22:40:16 +0000

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smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);

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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);

Eric Biederman

2003-07-21 20:13:45 +0000

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/* There is no extension information... */

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/* Compute the checksums */

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mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);

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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);

Stefan Reinauer

2010-03-22 11:42:32 +0000

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printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",

Eric Biederman

2003-07-21 20:13:45 +0000

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mc, smp_next_mpe_entry(mc));

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return smp_next_mpe_entry(mc);

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}

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Yinghai Lu

2004-10-20 05:07:16 +0000

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unsigned long write_smp_table(unsigned long addr)

Eric Biederman

2003-07-21 20:13:45 +0000

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{

208

void *v;

209

v = smp_write_floating_table(addr);

Yinghai Lu

2004-10-20 05:07:16 +0000

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return (unsigned long)smp_write_config_table(v);

Eric Biederman