Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com> |
| 5 | * |
| 6 | * Copyright (C) 2006 AMD |
| 7 | * Written by Yinghai Lu <yinghailu@gmail.com> for AMD. |
| 8 | * |
| 9 | * Copyright (C) 2007 University of Mannheim |
| 10 | * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim |
| 11 | * |
| 12 | * Copyright (C) 2009 University of Heidelberg |
| 13 | * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License as published by |
| 17 | * the Free Software Foundation; either version 2 of the License, or |
| 18 | * (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 28 | */ |
| 29 | |
| 30 | #include <console/console.h> |
| 31 | #include <arch/smp/mpspec.h> |
| 32 | #include <arch/io.h> |
| 33 | #include <device/pci.h> |
| 34 | #include <string.h> |
| 35 | #include <stdint.h> |
| 36 | #if CONFIG_LOGICAL_CPUS==1 |
| 37 | #include <cpu/amd/multicore.h> |
| 38 | #endif |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 39 | #include <cpu/amd/amdfam10_sysconf.h> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 40 | #include "mb_sysconf.h" |
| 41 | |
| 42 | static void *smp_write_config_table(void *v) |
| 43 | { |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 44 | struct mp_config_table *mc; |
| 45 | int isa_bus; |
| 46 | |
| 47 | struct mb_sysconf_t *m; |
| 48 | |
| 49 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 50 | |
Uwe Hermann | 55dc223 | 2010-10-25 15:32:07 +0000 | [diff] [blame] | 51 | mptable_init(mc, "DL165 G6 ", LAPIC_ADDR); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 52 | |
| 53 | smp_write_processors(mc); |
| 54 | |
| 55 | get_bus_conf(); |
| 56 | m = sysconf.mb; |
| 57 | |
| 58 | mptable_write_buses(mc, NULL, &isa_bus); |
| 59 | printk(BIOS_DEBUG, "writing %d as ISA to mptable (%d for real)...\n", isa_bus, m->bus_isa); |
| 60 | |
| 61 | /*I/O APICs: APIC ID Version State Address*/ |
| 62 | { |
| 63 | device_t dev = 0; |
| 64 | int i; |
| 65 | struct resource *res; |
| 66 | for(i=0; i<3; i++) { |
| 67 | dev = dev_find_device(0x1166, 0x0235, dev); |
| 68 | if (dev) { |
| 69 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 70 | if (res) { |
| 71 | printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base); |
| 72 | smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); |
| 73 | } |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | } |
| 78 | |
| 79 | /* IRQ routing as factory BIOS */ |
| 80 | outb(0x00, 0xc00); outb(0x09, 0xc01); |
| 81 | outb(0x01, 0xc00); outb(0x0a, 0xc01); |
| 82 | outb(0x02, 0xc00); outb(0x0e, 0xc01); |
| 83 | outb(0x03, 0xc00); outb(0x07, 0xc01); |
| 84 | outb(0x07, 0xc00); outb(0x05, 0xc01); |
| 85 | |
| 86 | // 8259 registers... |
| 87 | outb(0xa0, 0x4d0); |
| 88 | outb(0x0e, 0x4d1); |
| 89 | |
| 90 | { |
| 91 | device_t dev; |
| 92 | dev = dev_find_device(0x1166, 0x0205, 0); |
| 93 | if(dev) { |
| 94 | uint32_t dword; |
| 95 | dword = pci_read_config32(dev, 0x64); |
| 96 | dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 |
| 97 | pci_write_config32(dev, 0x64, dword); |
| 98 | } |
| 99 | // set GEVENT pins to NO OP |
| 100 | /* outb(0x33, 0xcd6); outb(0x00, 0xcd7); |
| 101 | outb(0x34, 0xcd6); outb(0x00, 0xcd7); |
| 102 | outb(0x35, 0xcd6); outb(0x00, 0xcd7); */ |
| 103 | } |
| 104 | |
| 105 | // hide XIOAPIC PCI configuration space |
| 106 | { |
| 107 | device_t dev; |
| 108 | dev = dev_find_device(0x1166, 0x205, 0); |
| 109 | if (dev) { |
| 110 | uint32_t dword; |
| 111 | dword = pci_read_config32(dev, 0x64); |
| 112 | dword |= (1<<26); |
| 113 | pci_write_config32(dev, 0x64, dword); |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0); |
| 118 | |
| 119 | /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ |
| 120 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0, m->apicid_bcm5785[0], 0x5); |
| 121 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0, m->apicid_bcm5785[0], 0xa); |
| 122 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0x4); |
| 123 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0x3); |
| 124 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0x2); |
| 125 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0x1); |
| 126 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0x0); |
| 127 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0, m->apicid_bcm5785[2], 0x8); |
| 128 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1, m->apicid_bcm5785[2], 0x7); |
| 129 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0, m->apicid_bcm5785[2], 0xa); |
| 130 | |
| 131 | /* enable int */ |
| 132 | /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ |
| 133 | { |
| 134 | device_t dev; |
| 135 | dev = dev_find_device(0x1166, 0x0205, 0); |
| 136 | if(dev) { |
| 137 | uint32_t dword; |
| 138 | dword = pci_read_config32(dev, 0x6c); |
| 139 | dword |= (1<<4); // enable interrupts |
| 140 | printk(BIOS_DEBUG, "6ch: %x\n",dword); |
| 141 | pci_write_config32(dev, 0x6c, dword); |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ |
Tobias Diedrich | b907d32 | 2010-10-26 22:40:16 +0000 | [diff] [blame^] | 146 | smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); |
| 147 | smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 148 | |
| 149 | //extended table entries |
| 150 | smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); |
| 151 | smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); |
| 152 | smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); |
| 153 | smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0); |
| 154 | smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f); |
| 155 | smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006); |
| 156 | smp_write_bus_hierarchy(mc, 8, 0x01, 0); |
| 157 | smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); |
| 158 | smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); |
| 159 | |
| 160 | |
| 161 | /* Compute the checksums */ |
| 162 | mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 163 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 164 | printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", |
| 165 | mc, smp_next_mpe_entry(mc)); |
| 166 | return smp_next_mpe_entry(mc); |
| 167 | } |
| 168 | |
| 169 | unsigned long write_smp_table(unsigned long addr) |
| 170 | { |
| 171 | void *v; |
| 172 | v = smp_write_floating_table(addr); |
| 173 | return (unsigned long)smp_write_config_table(v); |
| 174 | } |