blob: 8268bd516fa23244a9b307de1981df726b12269b [file] [log] [blame]
Subrata Banikb8df6892019-11-01 18:26:56 +05301/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2019 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <soc/gpe.h>
17
18/* XHCI Controller 0:14.0 */
19
20Device (XHCI)
21{
22 Name (_ADR, 0x00140000)
23
24 Name (_PRW, Package () { GPE0_PME_B0, 3 })
25
26 Name (_S3D, 3) /* D3 supported in S3 */
27 Name (_S0W, 3) /* D3 can wake device in S0 */
28 Name (_S3W, 3) /* D3 can wake system from S3 */
29
30 Method (_PS0, 0, Serialized)
31 {
32
33 }
34
35 Method (_PS3, 0, Serialized)
36 {
37
38 }
39
40 /* Root Hub for Tigerlake-LP PCH */
41 Device (RHUB)
42 {
43 Name (_ADR, Zero)
44
45 /* USB2 */
46 Device (HS01) { Name (_ADR, 1) }
47 Device (HS02) { Name (_ADR, 2) }
48 Device (HS03) { Name (_ADR, 3) }
49 Device (HS04) { Name (_ADR, 4) }
50 Device (HS05) { Name (_ADR, 5) }
51 Device (HS06) { Name (_ADR, 6) }
52 Device (HS07) { Name (_ADR, 7) }
53 Device (HS08) { Name (_ADR, 8) }
54 Device (HS09) { Name (_ADR, 9) }
55 Device (HS10) { Name (_ADR, 10) }
56 Device (HS11) { Name (_ADR, 11) }
57 Device (HS12) { Name (_ADR, 12) }
58
59 /* USBr */
60 Device (USR1) { Name (_ADR, 11) }
61 Device (USR2) { Name (_ADR, 12) }
62
63 /* USB3 */
64 Device (SS01) { Name (_ADR, 13) }
65 Device (SS02) { Name (_ADR, 14) }
66 Device (SS03) { Name (_ADR, 15) }
67 Device (SS04) { Name (_ADR, 16) }
68 Device (SS05) { Name (_ADR, 17) }
69 Device (SS06) { Name (_ADR, 18) }
70 }
71}