Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame^] | 18 | * Foundation, Inc. |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | |
| 22 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 23 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 24 | |
| 25 | Name(_ADR, 0) |
| 26 | Name(_BBN, 0) |
| 27 | |
| 28 | Device (MCHC) |
| 29 | { |
| 30 | Name(_ADR, 0x00000000) // 0:0.0 |
| 31 | |
| 32 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 33 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 34 | { |
| 35 | Offset (0x40), // EPBAR |
| 36 | EPEN, 1, // Enable |
| 37 | , 11, // |
| 38 | EPBR, 24, // EPBAR |
| 39 | |
| 40 | Offset (0x48), // MCHBAR |
| 41 | MHEN, 1, // Enable |
| 42 | , 13, // |
| 43 | MHBR, 22, // MCHBAR |
| 44 | |
| 45 | Offset (0x60), // PCIe BAR |
| 46 | PXEN, 1, // Enable |
| 47 | PXSZ, 2, // BAR size |
| 48 | , 23, // |
| 49 | PXBR, 10, // PCIe BAR |
| 50 | |
| 51 | Offset (0x68), // DMIBAR |
| 52 | DMEN, 1, // Enable |
| 53 | , 11, // |
| 54 | DMBR, 24, // DMIBAR |
| 55 | |
| 56 | |
| 57 | Offset (0xa0), |
| 58 | TOM, 16, |
| 59 | TUUD, 16, |
| 60 | |
| 61 | Offset (0xb0), // Top of Low Used Memory |
| 62 | TLUD, 16, |
| 63 | } |
| 64 | |
| 65 | Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ |
| 66 | Name (CTCC, 0) /* CTDP Current Selection */ |
| 67 | Name (CTCN, 0) /* CTDP Nominal Select */ |
| 68 | Name (CTCD, 1) /* CTDP Down Select */ |
| 69 | Name (CTCU, 2) /* CTDP Up Select */ |
| 70 | |
| 71 | OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) |
| 72 | Field (MCHB, DWordAcc, Lock, Preserve) |
| 73 | { |
| 74 | Offset (0x5930), |
| 75 | CTDN, 15, /* CTDP Nominal PL1 */ |
| 76 | Offset (0x59a0), |
| 77 | PL1V, 15, /* Power Limit 1 Value */ |
| 78 | PL1E, 1, /* Power Limit 1 Enable */ |
| 79 | PL1C, 1, /* Power Limit 1 Clamp */ |
| 80 | PL1T, 7, /* Power Limit 1 Time */ |
| 81 | Offset (0x59a4), |
| 82 | PL2V, 15, /* Power Limit 2 Value */ |
| 83 | PL2E, 1, /* Power Limit 2 Enable */ |
| 84 | PL2C, 1, /* Power Limit 2 Clamp */ |
| 85 | PL2T, 7, /* Power Limit 2 Time */ |
| 86 | Offset (0x5f3c), |
| 87 | TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ |
| 88 | Offset (0x5f40), |
| 89 | CTDD, 15, /* CTDP Down PL1 */ |
| 90 | , 1, |
| 91 | TARD, 8, /* CTDP Down Turbo Activation Ratio */ |
| 92 | Offset (0x5f48), |
| 93 | CTDU, 15, /* CTDP Up PL1 */ |
| 94 | , 1, |
| 95 | TARU, 8, /* CTDP Up Turbo Activation Ratio */ |
| 96 | Offset (0x5f50), |
| 97 | CTCS, 2, /* CTDP Select */ |
| 98 | Offset (0x5f54), |
| 99 | TARS, 8, /* Turbo Activation Ratio Select */ |
| 100 | } |
| 101 | |
| 102 | /* |
| 103 | * Search CPU0 _PSS looking for control=arg0 and then |
| 104 | * return previous P-state entry number for new _PPC |
| 105 | * |
| 106 | * Format of _PSS: |
| 107 | * Name (_PSS, Package () { |
| 108 | * Package (6) { freq, power, tlat, blat, control, status } |
| 109 | * } |
| 110 | */ |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 111 | External (\_PR.CP00._PSS) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 112 | Method (PSSS, 1, NotSerialized) |
| 113 | { |
| 114 | Store (One, Local0) /* Start at P1 */ |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 115 | Store (SizeOf (\_PR.CP00._PSS), Local1) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 116 | |
| 117 | While (LLess (Local0, Local1)) { |
| 118 | /* Store _PSS entry Control value to Local2 */ |
| 119 | ShiftRight (DeRefOf (Index (DeRefOf (Index |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 120 | (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 121 | If (LEqual (Local2, Arg0)) { |
| 122 | Return (Subtract (Local0, 1)) |
| 123 | } |
| 124 | Increment (Local0) |
| 125 | } |
| 126 | |
| 127 | Return (0) |
| 128 | } |
| 129 | |
| 130 | /* Set TDP Down */ |
| 131 | Method (STND, 0, Serialized) |
| 132 | { |
| 133 | If (Acquire (CTCM, 100)) { |
| 134 | Return (0) |
| 135 | } |
| 136 | If (LEqual (CTCD, CTCC)) { |
| 137 | Release (CTCM) |
| 138 | Return (0) |
| 139 | } |
| 140 | |
| 141 | Store ("Set TDP Down", Debug) |
| 142 | |
| 143 | /* Set CTC */ |
| 144 | Store (CTCD, CTCS) |
| 145 | |
| 146 | /* Set TAR */ |
| 147 | Store (TARD, TARS) |
| 148 | |
| 149 | /* Set PPC limit and notify OS */ |
| 150 | Store (PSSS (TARD), PPCM) |
| 151 | PPCN () |
| 152 | |
| 153 | /* Set PL2 to 1.25 * PL1 */ |
| 154 | Divide (Multiply (CTDD, 125), 100, Local0, PL2V) |
| 155 | |
| 156 | /* Set PL1 */ |
| 157 | Store (CTDD, PL1V) |
| 158 | |
| 159 | /* Store the new TDP Down setting */ |
| 160 | Store (CTCD, CTCC) |
| 161 | |
| 162 | Release (CTCM) |
| 163 | Return (1) |
| 164 | } |
| 165 | |
| 166 | /* Set TDP Nominal from Down */ |
| 167 | Method (STDN, 0, Serialized) |
| 168 | { |
| 169 | If (Acquire (CTCM, 100)) { |
| 170 | Return (0) |
| 171 | } |
| 172 | If (LEqual (CTCN, CTCC)) { |
| 173 | Release (CTCM) |
| 174 | Return (0) |
| 175 | } |
| 176 | |
| 177 | Store ("Set TDP Nominal", Debug) |
| 178 | |
| 179 | /* Set PL1 */ |
| 180 | Store (CTDN, PL1V) |
| 181 | |
| 182 | /* Set PL2 to 1.25 * PL1 */ |
| 183 | Divide (Multiply (CTDN, 125), 100, Local0, PL2V) |
| 184 | |
| 185 | /* Set PPC limit and notify OS */ |
| 186 | Store (PSSS (TARN), PPCM) |
| 187 | PPCN () |
| 188 | |
| 189 | /* Set TAR */ |
| 190 | Store (TARN, TARS) |
| 191 | |
| 192 | /* Set CTC */ |
| 193 | Store (CTCN, CTCS) |
| 194 | |
| 195 | /* Store the new TDP Nominal setting */ |
| 196 | Store (CTCN, CTCC) |
| 197 | |
| 198 | Release (CTCM) |
| 199 | Return (1) |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | // Current Resource Settings |
| 204 | |
| 205 | Method (_CRS, 0, Serialized) |
| 206 | { |
| 207 | Name (MCRS, ResourceTemplate() |
| 208 | { |
| 209 | // Bus Numbers |
| 210 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 211 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 212 | |
| 213 | // IO Region 0 |
| 214 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 215 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 216 | |
| 217 | // PCI Config Space |
| 218 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 219 | |
| 220 | // IO Region 1 |
| 221 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 222 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 223 | |
| 224 | // VGA memory (0xa0000-0xbffff) |
| 225 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 226 | Cacheable, ReadWrite, |
| 227 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 228 | 0x00020000,,, ASEG) |
| 229 | |
| 230 | // OPROM reserved (0xc0000-0xc3fff) |
| 231 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 232 | Cacheable, ReadWrite, |
| 233 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 234 | 0x00004000,,, OPR0) |
| 235 | |
| 236 | // OPROM reserved (0xc4000-0xc7fff) |
| 237 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 238 | Cacheable, ReadWrite, |
| 239 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 240 | 0x00004000,,, OPR1) |
| 241 | |
| 242 | // OPROM reserved (0xc8000-0xcbfff) |
| 243 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 244 | Cacheable, ReadWrite, |
| 245 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 246 | 0x00004000,,, OPR2) |
| 247 | |
| 248 | // OPROM reserved (0xcc000-0xcffff) |
| 249 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 250 | Cacheable, ReadWrite, |
| 251 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 252 | 0x00004000,,, OPR3) |
| 253 | |
| 254 | // OPROM reserved (0xd0000-0xd3fff) |
| 255 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 256 | Cacheable, ReadWrite, |
| 257 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 258 | 0x00004000,,, OPR4) |
| 259 | |
| 260 | // OPROM reserved (0xd4000-0xd7fff) |
| 261 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 262 | Cacheable, ReadWrite, |
| 263 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 264 | 0x00004000,,, OPR5) |
| 265 | |
| 266 | // OPROM reserved (0xd8000-0xdbfff) |
| 267 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 268 | Cacheable, ReadWrite, |
| 269 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 270 | 0x00004000,,, OPR6) |
| 271 | |
| 272 | // OPROM reserved (0xdc000-0xdffff) |
| 273 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 274 | Cacheable, ReadWrite, |
| 275 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 276 | 0x00004000,,, OPR7) |
| 277 | |
| 278 | // BIOS Extension (0xe0000-0xe3fff) |
| 279 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 280 | Cacheable, ReadWrite, |
| 281 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 282 | 0x00004000,,, ESG0) |
| 283 | |
| 284 | // BIOS Extension (0xe4000-0xe7fff) |
| 285 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 286 | Cacheable, ReadWrite, |
| 287 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 288 | 0x00004000,,, ESG1) |
| 289 | |
| 290 | // BIOS Extension (0xe8000-0xebfff) |
| 291 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 292 | Cacheable, ReadWrite, |
| 293 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 294 | 0x00004000,,, ESG2) |
| 295 | |
| 296 | // BIOS Extension (0xec000-0xeffff) |
| 297 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 298 | Cacheable, ReadWrite, |
| 299 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 300 | 0x00004000,,, ESG3) |
| 301 | |
| 302 | // System BIOS (0xf0000-0xfffff) |
| 303 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 304 | Cacheable, ReadWrite, |
| 305 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 306 | 0x00010000,,, FSEG) |
| 307 | |
| 308 | // PCI Memory Region (Top of memory-0xfebfffff) |
| 309 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 310 | Cacheable, ReadWrite, |
| 311 | 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, |
| 312 | 0xfec00000,,, PM01) |
| 313 | |
| 314 | // TPM Area (0xfed40000-0xfed44fff) |
| 315 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 316 | Cacheable, ReadWrite, |
| 317 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 318 | 0x00005000,,, TPMR) |
| 319 | }) |
| 320 | |
| 321 | // Find PCI resource area in MCRS |
| 322 | CreateDwordField(MCRS, PM01._MIN, PMIN) |
| 323 | CreateDwordField(MCRS, PM01._MAX, PMAX) |
| 324 | CreateDwordField(MCRS, PM01._LEN, PLEN) |
| 325 | |
| 326 | // Fix up PCI memory region |
| 327 | // Start with Top of Lower Usable DRAM |
| 328 | Store (^MCHC.TLUD, Local0) |
| 329 | ShiftRight (Local0, 4, Local0) |
| 330 | Store (^MCHC.TUUD, Local1) |
| 331 | |
| 332 | // Check if ME base is equal |
| 333 | If (LEqual (Local0, Local1)) { |
| 334 | // Use Top Of Memory instead |
| 335 | Store (^MCHC.TOM, Local0) |
| 336 | ShiftRight (Local0, 6, Local0) |
| 337 | } |
| 338 | |
| 339 | ShiftLeft (Local0, 20, Local0) |
| 340 | Store (Local0, PMIN) |
| 341 | Add(Subtract(PMAX, PMIN), 1, PLEN) |
| 342 | |
| 343 | Return (MCRS) |
| 344 | } |