Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mns3kb.c |
| 6 | * |
| 7 | * KB memory specific function to support S3 resume |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/NB/KB) |
| 12 | * @e \$Revision: 87696 $ @e \$Date: 2013-02-07 12:35:03 -0600 (Thu, 07 Feb 2013) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | /* |
| 46 | *---------------------------------------------------------------------------- |
| 47 | * MODULES USED |
| 48 | * |
| 49 | *---------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | |
| 53 | |
| 54 | #include "AGESA.h" |
| 55 | #include "AdvancedApi.h" |
| 56 | #include "amdlib.h" |
| 57 | #include "Ids.h" |
| 58 | #include "OptionMemory.h" |
| 59 | #include "mm.h" |
| 60 | #include "mn.h" |
| 61 | #include "S3.h" |
| 62 | #include "mfs3.h" |
| 63 | #include "mnkb.h" |
| 64 | #include "cpuRegisters.h" |
| 65 | #include "cpuFamRegisters.h" |
| 66 | #include "cpuFamilyTranslation.h" |
| 67 | #include "mnS3kb.h" |
| 68 | #include "heapManager.h" |
| 69 | #include "Filecode.h" |
| 70 | CODE_GROUP (G3_DXE) |
| 71 | RDATA_GROUP (G3_DXE) |
| 72 | |
| 73 | #define FILECODE PROC_MEM_NB_KB_MNS3KB_FILECODE |
| 74 | #define DCT0_MEMPSTATE_MASK 0x10 |
| 75 | #define DCT1_MEMPSTATE_MASK 0x20 |
| 76 | #define DO_NOT_CARE 0 |
| 77 | /*---------------------------------------------------------------------------- |
| 78 | * TYPEDEFS AND STRUCTURES |
| 79 | * |
| 80 | *---------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | /*---------------------------------------------------------------------------- |
| 84 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 85 | * |
| 86 | *---------------------------------------------------------------------------- |
| 87 | */ |
| 88 | UINT16 |
| 89 | STATIC |
| 90 | MemNS3GetRegLstPtrKB ( |
| 91 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 92 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 93 | ); |
| 94 | |
| 95 | AGESA_STATUS |
| 96 | STATIC |
| 97 | MemNS3GetDeviceRegLstKB ( |
| 98 | IN UINT32 RegisterLstID, |
| 99 | OUT VOID **RegisterHeader |
| 100 | ); |
| 101 | |
| 102 | VOID |
| 103 | STATIC |
| 104 | MemNS3SetDfltPhyRegKB ( |
| 105 | IN ACCESS_WIDTH AccessWidth, |
| 106 | IN PCI_ADDR Address, |
| 107 | IN VOID *Value, |
| 108 | IN OUT VOID *ConfigPtr |
| 109 | ); |
| 110 | |
| 111 | VOID |
| 112 | STATIC |
| 113 | MemNS3SetDynModeChangeKB ( |
| 114 | IN ACCESS_WIDTH AccessWidth, |
| 115 | IN PCI_ADDR Address, |
| 116 | IN OUT VOID *Value, |
| 117 | IN OUT VOID *ConfigPtr |
| 118 | ); |
| 119 | |
| 120 | VOID |
| 121 | STATIC |
| 122 | MemNS3SetPhyStatusRegKB ( |
| 123 | IN ACCESS_WIDTH AccessWidth, |
| 124 | IN PCI_ADDR Address, |
| 125 | IN OUT VOID *Value, |
| 126 | IN OUT VOID *ConfigPtr |
| 127 | ); |
| 128 | |
| 129 | VOID |
| 130 | STATIC |
| 131 | MemNS3DisableChannelKB ( |
| 132 | IN ACCESS_WIDTH AccessWidth, |
| 133 | IN PCI_ADDR Address, |
| 134 | IN OUT VOID *Value, |
| 135 | IN OUT VOID *ConfigPtr |
| 136 | ); |
| 137 | |
| 138 | VOID |
| 139 | STATIC |
| 140 | MemNS3GetConPCIMaskKB ( |
| 141 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 142 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 143 | ); |
| 144 | |
| 145 | VOID |
| 146 | STATIC |
| 147 | MemNS3ChangeMemPStateContextAndFlowNb ( |
| 148 | IN ACCESS_WIDTH AccessWidth, |
| 149 | IN PCI_ADDR Address, |
| 150 | IN OUT VOID *Value, |
| 151 | IN OUT VOID *ConfigPtr |
| 152 | ); |
| 153 | |
| 154 | VOID |
| 155 | STATIC |
| 156 | MemNS3GetCSRKB ( |
| 157 | IN ACCESS_WIDTH AccessWidth, |
| 158 | IN PCI_ADDR Address, |
| 159 | IN VOID *Value, |
| 160 | IN OUT VOID *ConfigPtr |
| 161 | ); |
| 162 | |
| 163 | VOID |
| 164 | STATIC |
| 165 | MemNS3SetCSRKB ( |
| 166 | IN ACCESS_WIDTH AccessWidth, |
| 167 | IN PCI_ADDR Address, |
| 168 | IN OUT VOID *Value, |
| 169 | IN OUT VOID *ConfigPtr |
| 170 | ); |
| 171 | |
| 172 | VOID |
| 173 | STATIC |
| 174 | MemNS3SetPhyFenceKB ( |
| 175 | IN ACCESS_WIDTH AccessWidth, |
| 176 | IN PCI_ADDR Address, |
| 177 | IN VOID *Value, |
| 178 | IN OUT VOID *ConfigPtr |
| 179 | ); |
| 180 | |
| 181 | BOOLEAN |
| 182 | MemS3ResumeConstructNBBlockKB ( |
| 183 | IN OUT VOID *S3NBPtr, |
| 184 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 185 | IN UINT8 NodeID |
| 186 | ); |
| 187 | |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 188 | VOID |
| 189 | MemNS3SetMemClkFreqValKB ( |
| 190 | IN ACCESS_WIDTH AccessWidth, |
| 191 | IN PCI_ADDR Address, |
| 192 | IN OUT VOID *Value, |
| 193 | IN OUT VOID *ConfigPtr |
| 194 | ); |
| 195 | |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 196 | /*---------------------------------------------------------------------------- |
| 197 | * DEFINITIONS AND MACROS |
| 198 | * |
| 199 | *---------------------------------------------------------------------------- |
| 200 | */ |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 201 | CONST PCI_SPECIAL_CASE PciSpecialCaseFuncKB[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 202 | {MemNS3GetCSRKB, MemNS3SetCSRKB}, |
| 203 | {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, |
| 204 | {MemNS3GetNBPStateDepRegUnb, MemNS3SetNBPStateDepRegUnb}, |
| 205 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPhyRegKB}, |
| 206 | {MemNS3ChangeMemPStateContextAndFlowNb, MemNS3ChangeMemPStateContextAndFlowNb}, |
| 207 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeKB}, |
| 208 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3DisableChannelKB}, |
| 209 | {MemNS3SaveNBRegisterUnb, MemNS3RestoreNBRegisterUnb}, |
| 210 | {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb}, |
| 211 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetPhyStatusRegKB}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 212 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValKB}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 213 | {MemNS3ChangeMemPStateContextNb, MemNS3ChangeMemPStateContextNb}, |
| 214 | {MemNS3GetBitFieldNb, MemNS3SetPhyFenceKB}, |
| 215 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ReleaseNBPSUnb}, |
| 216 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ForceNBP0Unb}, |
| 217 | {MemNSaveHobDataUnb, MemNRestoreHobDataUnb} |
| 218 | }; |
| 219 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 220 | CONST MSR_SPECIAL_CASE MsrSpecialCaseFuncKB[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 221 | { MemNModdifyMtrrFixDramModEn, MemNModdifyMtrrFixDramModEn} |
| 222 | }; |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 223 | CONST PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 224 | {{14,3, 1}, DO_NOT_CARE, 0, 0}, |
| 225 | {{0, 0, 0}, FUNC_2, 0x110, 0x00000020}, |
| 226 | {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703}, |
| 227 | {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0707}, |
| 228 | {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 229 | {{0, 0, 0}, FUNC_1, 0x120, 0x001FFFFF}, |
| 230 | {{0, 0, 0}, FUNC_1, 0x124, 0x001FFFFF}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 231 | {{0, 0, 0}, FUNC_1, 0x200, 0x00FFF87B}, |
| 232 | {{0, 0, 0}, FUNC_1, 0x204, 0x00FFF800}, |
| 233 | {{0, 0, 0}, FUNC_2, 0x114, 0x00000200}, |
| 234 | {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, |
| 235 | {{0, 0, 0}, FUNC_2, 0x11C, 0xAFFFFFFF}, |
| 236 | {{0, 0, 0}, FUNC_2, 0x120, 0x00FFFFFF}, |
| 237 | {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}, |
| 238 | {{0, 0, 0}, FUNC_2, 0x1B4, 0xFC7FFFFF}, |
| 239 | {{0, 0, 0}, FUNC_2, 0x1BC, 0xFFFFFFFF}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 240 | {{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900} |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = { |
| 244 | 0, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 245 | ARRAY_SIZE(S3PciPreSelfRefDescriptorKB), |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 246 | S3PciPreSelfRefDescriptorKB, |
| 247 | PciSpecialCaseFuncKB |
| 248 | }; |
| 249 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 250 | CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorKB[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 251 | // DCT 0 |
| 252 | {{7, 0, 1}, DCT0, 0x40, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 253 | {{7, 0, 1}, DCT0, 0x44, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 254 | {{7, 0, 1}, DCT0, 0x48, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 255 | {{7, 0, 1}, DCT0, 0x4C, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 256 | {{7, 0, 1}, DCT0, 0x60, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 257 | {{7, 0, 1}, DCT0, 0x64, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 258 | {{7, 0, 1}, DCT0, 0x78, 0x00020000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 259 | {{7, 2, 1}, DCT0, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 260 | {{7, 0, 1}, DCT0, 0x84, 0x00800003, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 261 | {{7, 0, 1}, DCT0, 0x88, 0x3F000000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 262 | {{7, 0, 1}, DCT0, 0x8C, 0x00070000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 263 | {{7, 0, 1}, DCT0, 0x90, 0x0BFF0000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 264 | {{7, 0, 1}, DCT0, 0xA8, 0x9C730000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 265 | {{7, 0, 1}, DCT0, 0x1BC, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 266 | {{7, 0, 1}, DCT0, 0x200, 0x3F1F1F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 267 | {{7, 0, 1}, DCT0, 0x204, 0x0F3F0F3F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 268 | {{7, 0, 1}, DCT0, 0x208, 0x07070707, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 269 | {{7, 0, 1}, DCT0, 0x20C, 0x00030F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 270 | {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFC7000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 271 | {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, |
| 272 | {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, |
| 273 | {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, |
| 274 | {{7, 0, 1}, DCT0, 0x214, 0x000F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 275 | {{7, 0, 1}, DCT0, 0x218, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 276 | {{7, 0, 1}, DCT0, 0x21C, 0x001F1F00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 277 | {{7, 2, 1}, DCT0, 0x220, 0x00001F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 278 | {{7, 2, 1}, DCT0, 0x224, 0x0000070F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 279 | {{7, 0, 1}, DCT0, 0x228, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 280 | {{7, 1, 1}, DCT0, 0x22C, 0x0000001F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 281 | {{7, 0, 1}, DCT0, 0x230, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 282 | {{7, 0, 1}, DCT0, 0x234, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 283 | {{7, 0, 1}, DCT0, 0x238, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 284 | {{7, 0, 1}, DCT0, 0x23C, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 285 | {{7, 2, 1}, DCT0, 0x240, 0x000077FF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 286 | {{7, 1, 1}, DCT0, 0x244, 0x0000000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 287 | {{7, 0, 1}, DCT0, 0x248, 0xBF3F1F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 288 | {{7, 0, 1}, DCT0, 0x24C, 0x3F3F3F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 289 | {{7, 0, 1}, DCT0, 0x2E0, 0x5F700000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 290 | {{7, 0, 1}, DCT0, 0x2E8, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 291 | {{7, 2, 1}, DCT0, 0x2EC, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 292 | {{7, 1, 1}, DCT0, 0x2F0, 0x00000001, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 293 | {{7, 2, 1}, DCT0, 0x400, 0x00000F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 294 | {{7, 0, 1}, DCT0, 0x404, 0x8F1F0F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 295 | {{7, 0, 1}, DCT0, 0x408, 0x1F000007, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 296 | {{7, 2, 1}, DCT0, 0x420, 0x00000F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 297 | |
| 298 | // Phy Initialization |
| 299 | // 1. Program D18F2x9C_x0D0F_E013_dct[1:0] = 0118h. |
| 300 | {{1, 2, 1}, DCT0, BFPllRegWaitTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 301 | // 2. Force the phy to M0 with the following sequence: |
| 302 | // A. Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 190h. |
| 303 | {{3, 3, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 304 | // B. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80800000h. |
| 305 | {{9, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 306 | // C. Program D18F2x9C_x0000_000B_dct[0] = 40000000h. |
| 307 | // D. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80000000h |
| 308 | {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 309 | |
| 310 | // 3. Phy voltage related |
| 311 | {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, |
| 312 | {{1, 1, 1}, DCT0, BFClkRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, |
| 313 | {{1, 2, 1}, DCT0, BFCmpVioLvl, 0x0000C000, DCT0_MASK, ANY_DIMM_MASK}, |
| 314 | {{1, 1, 1}, DCT0, BFCmdRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, |
| 315 | {{1, 1, 1}, DCT0, BFCsrComparator, 0x0000000C, DCT0_MASK, ANY_DIMM_MASK}, |
| 316 | {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, |
| 317 | {{1, 1, 1}, DCT0, BFObsrvVrefSel, 0x00000007, DCT0_MASK, ANY_DIMM_MASK}, |
| 318 | |
| 319 | // 4. Frequency Change |
| 320 | // Check if a channel needs to be disabled |
| 321 | {{1, 1, 1}, DCT0, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 322 | {{6, 3, 1}, DCT0, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 323 | {{1, 1, 1}, DCT0, BFPhyClkConfig0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 324 | {{1, 1, 1}, DCT0, BFPhyClkConfig1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 325 | |
| 326 | {{7, 0, 1}, DCT0, 0x94, 0x9FF1CC1F, DCT0_MASK, ANY_DIMM_MASK}, |
| 327 | {{1, 2, 1}, DCT0, BFPOdtOff, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 328 | |
| 329 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, |
| 330 | {{1, 2, 1}, DCT0, BFProcOdtAdv, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 331 | {{1, 2, 1}, DCT0, BFReducedLoop, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 332 | |
| 333 | // Enable MemClk |
| 334 | {{10, 0, 1}, DCT0, 0x94, 0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 335 | {{1, 2, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 336 | // Hardware programs POdtOff for the current M-state (D18F2x9C_x0D0F_E006_dct[0][PhyPS]) with the value in D18F2x94_dct[0] |
| 337 | // [ProcOdtDis] (via D18F2x9C_x0000_000B_dct[0][ProcOdtDis]) when the memory frequency is updated. BIOS must reprogram this |
| 338 | // BIOS must reprogram this field after each frequency change if the target value differs from D18F2x94_dct[0][ProcOdtDis]. |
| 339 | {{1, 2, 1}, DCT0, BFPOdtOff, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 340 | |
| 341 | // DCT 0 |
| 342 | // 5. Phy Fence |
| 343 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 344 | {{1, 2, 1}, DCT0, BFDataFence2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 345 | {{1, 2, 1}, DCT0, BFFence2, 0x00007C1F, DCT0_MASK, ANY_DIMM_MASK}, |
| 346 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, |
| 347 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MASK, ANY_DIMM_MASK}, |
| 348 | // 6. Phy Compensation Init |
| 349 | {{3, 3, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 350 | {{1, 0, 1}, DCT0, BFPhy0x0D0F0F0B, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 351 | {{1, 0, 1}, DCT0, BFPhy0x0D0F0F07, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 352 | {{1, 0, 1}, DCT0, BFPhy0x0D0F0F03, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 353 | {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 354 | {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 355 | {{8, 2, 1}, DCT0, BFDataByteTxPreDriverCal, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 356 | {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 357 | {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 358 | {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 359 | {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 360 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 361 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 362 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad3, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 363 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad4, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 364 | {{8, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 365 | {{8, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 366 | {{8, 2, 1}, DCT0, BFAddrTxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 367 | {{8, 2, 1}, DCT0, BFClock0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 368 | {{8, 2, 1}, DCT0, BFClock1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 369 | |
| 370 | {{1, 1, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 371 | // Program MemPstate 1 registers |
| 372 | // Switch to MemPstate context 1 |
| 373 | {{11, 3, 1}, DO_NOT_CARE, 1, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 374 | {{1, 1, 1}, DCT0, BFRate, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 375 | {{1, 2, 1}, DCT0, BFProcOdtAdv, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 376 | {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 377 | {{7, 0, 1}, DCT0, 0x200, 0x3F1F1F1F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 378 | {{7, 0, 1}, DCT0, 0x204, 0x0F3F0F3F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 379 | {{7, 0, 1}, DCT0, 0x208, 0x07070707, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 380 | {{7, 0, 1}, DCT0, 0x20C, 0x00030F1F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 381 | {{7, 0, 1}, DCT0, 0x214, 0x000F0F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 382 | {{7, 0, 1}, DCT0, 0x218, 0x0F0F0F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 383 | {{7, 0, 1}, DCT0, 0x21C, 0x001F1F00, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 384 | {{7, 1, 1}, DCT0, 0x22C, 0x0000001F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 385 | {{7, 2, 1}, DCT0, 0x240, 0x000077FF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 386 | {{7, 0, 1}, DCT0, 0x248, 0xBF3F1F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 387 | {{7, 0, 1}, DCT0, 0x2E8, 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 388 | {{7, 2, 1}, DCT0, 0x2EC, 0x0000FFFF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 389 | // Compute Phy fence for MemPstate 1 |
| 390 | // DCT 0 |
| 391 | {{12, 2, 1}, DCT0, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 392 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 393 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 394 | |
| 395 | {{1, 1, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 396 | // Switch back to MemPstate context 0 |
| 397 | {{11, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 398 | |
| 399 | // Set Fence back to Fence of M0 to prepare for fine delay restore for M0 |
| 400 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 401 | {{1, 2, 1}, DCT0, BFDataFence2, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 402 | {{1, 2, 1}, DCT0, BFFence2, 0x00007C1F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 403 | |
| 404 | {{15, 0, 1}, S3_UMA_SIZE, 0, 0, ANY_DIMM_MASK, ANY_DIMM_MASK, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 405 | {{15, 0, 1}, S3_UMA_BASE, 0, 0, ANY_DIMM_MASK, ANY_DIMM_MASK, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 406 | {{15, 1, 1}, S3_UMA_MODE, 0, 0, ANY_DIMM_MASK, ANY_DIMM_MASK, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 407 | {{15, 0, 1}, S3_SUB_4G_CACHE_TOP, 0, 0, ANY_DIMM_MASK, ANY_DIMM_MASK, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 408 | {{15, 0, 1}, S3_SYSLIMIT, 0, 0, ANY_DIMM_MASK, ANY_DIMM_MASK, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 409 | // Always put UMA_ATTRIBUTE after other types for hob data save and restore |
| 410 | {{15, 0, 1}, S3_UMA_ATTRIBUTE, 0, 0, ANY_DIMM_MASK, ANY_DIMM_MASK, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 411 | |
| 412 | {{15, 1, 1}, S3_VDDIO, 0, 0, ANY_DIMM_MASK, ANY_DIMM_MASK, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE} |
| 413 | }; |
| 414 | |
| 415 | CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefKB = { |
| 416 | 0, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 417 | ARRAY_SIZE(S3CPciPreSelfDescriptorKB), |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 418 | S3CPciPreSelfDescriptorKB, |
| 419 | PciSpecialCaseFuncKB |
| 420 | }; |
| 421 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 422 | CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 423 | // DCT0 |
| 424 | {{12, 2, 1}, DCT0, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 425 | {{1, 2, 1}, DCT0, BFRxDqInsDly, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 426 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MASK, 0x01}, |
| 427 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MASK, 0x01}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 428 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000003FF, DCT0_MASK, 0x01}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 429 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MASK, 0x04}, |
| 430 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MASK, 0x04}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 431 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000003FF, DCT0_MASK, 0x04}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 432 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MASK, 0x10}, |
| 433 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MASK, 0x10}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 434 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000003FF, DCT0_MASK, 0x10}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 435 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MASK, 0x40}, |
| 436 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MASK, 0x40}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 437 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000003FF, DCT0_MASK, 0x40}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 438 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MASK, 0x01}, |
| 439 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MASK, 0x01}, |
| 440 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MASK, 0x04}, |
| 441 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x03FF03FF, DCT0_MASK, 0x04}, |
| 442 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x03FF03FF, DCT0_MASK, 0x10}, |
| 443 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x03FF03FF, DCT0_MASK, 0x10}, |
| 444 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x03FF03FF, DCT0_MASK, 0x40}, |
| 445 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MASK, 0x40}, |
| 446 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01}, |
| 447 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 448 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x000000FF, DCT0_MASK, 0x01}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 449 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04}, |
| 450 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 451 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MASK, 0x04}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 452 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10}, |
| 453 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 454 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MASK, 0x10}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 455 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40}, |
| 456 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 457 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MASK, 0x40}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 458 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01}, |
| 459 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01}, |
| 460 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04}, |
| 461 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04}, |
| 462 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MASK, 0x10}, |
| 463 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MASK, 0x10}, |
| 464 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MASK, 0x40}, |
| 465 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40}, |
| 466 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MASK, 0x01}, |
| 467 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MASK, 0x01}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 468 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_MASK, 0x01}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 469 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MASK, 0x04}, |
| 470 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MASK, 0x04}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 471 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_MASK, 0x04}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 472 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MASK, 0x10}, |
| 473 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MASK, 0x10}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 474 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_MASK, 0x10}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 475 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MASK, 0x40}, |
| 476 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MASK, 0x40}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 477 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_MASK, 0x40}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 478 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MASK, 0x01}, |
| 479 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MASK, 0x01}, |
| 480 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MASK, 0x04}, |
| 481 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_MASK, 0x04}, |
| 482 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_MASK, 0x10}, |
| 483 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_MASK, 0x10}, |
| 484 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_MASK, 0x40}, |
| 485 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_MASK, 0x40}, |
| 486 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MASK, ANY_DIMM_MASK}, |
| 487 | {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13, 0x00000083, DCT0_MASK, ANY_DIMM_MASK}, |
| 488 | {{1, 2, 1}, DCT0, BFDllCSRBiasTrim, 0x00007000, DCT0_MASK, ANY_DIMM_MASK}, |
| 489 | {{1, 2, 1}, DCT0, BFRxSsbMntClkEn, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 490 | {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 491 | {{1, 1, 1}, DCT0, BFEccDLLPwrDnConf, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 492 | {{1, 2, 1}, DCT0, BFTxPclkGateEn, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 493 | {{1, 1, 1}, DCT0, BFPchgPdPclkGateEn, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 494 | {{1, 1, 1}, DCT0, BFDataCtlPipePclkGateEn, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 495 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 496 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 497 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 498 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 499 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 500 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 501 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 502 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 503 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte8, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 504 | |
| 505 | {{11, 3, 1}, DO_NOT_CARE, 1, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 506 | |
| 507 | // DCT0 |
| 508 | {{12, 2, 1}, DCT0, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 509 | {{1, 2, 1}, DCT0, BFRxDqInsDly, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 510 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 511 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 512 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x01}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 513 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 514 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 515 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x04}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 516 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 517 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 518 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x10}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 519 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 520 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 521 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x40}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 522 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 523 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 524 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 525 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 526 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 527 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 528 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 529 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 530 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 531 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 532 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x01}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 533 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 534 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 535 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 536 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 537 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 538 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 539 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 540 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 541 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 542 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01}, |
| 543 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01}, |
| 544 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04}, |
| 545 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04}, |
| 546 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x10}, |
| 547 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x10}, |
| 548 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40}, |
| 549 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40}, |
| 550 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 551 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 552 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x01}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 553 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 554 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 555 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 556 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 557 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 558 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 559 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 560 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 561 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 562 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 563 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 564 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 565 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 566 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 567 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 568 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 569 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 570 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 571 | {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13, 0x00000083, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 572 | {{1, 2, 1}, DCT0, BFDllCSRBiasTrim, 0x00007000, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 573 | {{1, 2, 1}, DCT0, BFRxSsbMntClkEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 574 | {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 575 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 576 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 577 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 578 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 579 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 580 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 581 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 582 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 583 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte8, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 584 | |
| 585 | {{11, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 586 | |
| 587 | {{1, 1, 1}, DCT0, BFAddrCmdTri, 0x0000000A1, DCT0_MASK, ANY_DIMM_MASK}, |
| 588 | {{1, 1, 1}, DCT0, BFDisDllShutdownSR, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 589 | |
| 590 | {{1, 1, 1}, DCT0, BFVrefSel, 0x00000007, DCT0_MASK, ANY_DIMM_MASK}, |
| 591 | {{1, 2, 1}, DCT0, BFVrefDAC, 0x000001F8, DCT0_MASK, ANY_DIMM_MASK}, |
| 592 | |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 593 | {{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 594 | {{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 595 | {{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 596 | {{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 597 | {{0, 0, 0}, FUNC_2, 0x1B4, 0x08000000, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 598 | {{0, 0, 0}, FUNC_3, 0x180, 0x02000000, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 599 | {{0, 0, 0}, FUNC_3, 0x58, 0x0000001F, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 600 | {{0, 0, 0}, FUNC_3, 0x5C, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 601 | {{0, 0, 0}, FUNC_3, 0x44, 0x00400004, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 602 | |
| 603 | {{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 604 | {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK, S3_RESUME_MODE}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 605 | |
| 606 | {{13, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, ANY_DIMM_MASK, ANY_DIMM_MASK} |
| 607 | }; |
| 608 | |
| 609 | CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefKB = { |
| 610 | 0, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 611 | ARRAY_SIZE(S3CPciPostSelfDescriptorKB), |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 612 | S3CPciPostSelfDescriptorKB, |
| 613 | PciSpecialCaseFuncKB |
| 614 | }; |
| 615 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 616 | CONST MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorKB[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 617 | {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, |
| 618 | {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, |
| 619 | {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, |
| 620 | {{0, 0, 0}, 0xC001001F, 0x0044601080000600}, |
| 621 | {{0, 0, 1}, 0, 0, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 622 | {{0, 0, 0}, 0x250, 0x1F1F1F1F1F1F1F1F, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 623 | {{0, 0, 0}, 0x258, 0x1F1F1F1F1F1F1F1F, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 624 | {{0, 0, 1}, 1, 0, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 625 | {{0, 0, 0}, 0x00000200, 0x0000FFFFFFFFF007, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 626 | {{0, 0, 0}, 0x00000202, 0x0000FFFFFFFFF007, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 627 | {{0, 0, 0}, 0x00000204, 0x0000FFFFFFFFF007, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 628 | {{0, 0, 0}, 0x00000206, 0x0000FFFFFFFFF007, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 629 | {{0, 0, 0}, 0x00000208, 0x0000FFFFFFFFF007, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 630 | {{0, 0, 0}, 0x0000020A, 0x0000FFFFFFFFF007, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 631 | {{0, 0, 0}, 0x00000201, 0x0000FFFFFFFFF800, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 632 | {{0, 0, 0}, 0x00000203, 0x0000FFFFFFFFF800, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 633 | {{0, 0, 0}, 0x00000205, 0x0000FFFFFFFFF800, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 634 | {{0, 0, 0}, 0x00000207, 0x0000FFFFFFFFF800, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 635 | {{0, 0, 0}, 0x00000209, 0x0000FFFFFFFFF800, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE}, |
| 636 | {{0, 0, 0}, 0x0000020B, 0x0000FFFFFFFFF800, RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE} |
| 637 | }; |
| 638 | |
| 639 | CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefKB = { |
| 640 | 0, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 641 | ARRAY_SIZE(S3MSRPreSelfRefDescriptorKB), |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 642 | S3MSRPreSelfRefDescriptorKB, |
| 643 | MsrSpecialCaseFuncKB |
| 644 | }; |
| 645 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 646 | VOID * CONST MemS3RegListKB[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 647 | (VOID *)&S3PciPreSelfRefKB, |
| 648 | NULL, |
| 649 | (VOID *)&S3CPciPreSelfRefKB, |
| 650 | (VOID *)&S3CPciPostSelfRefKB, |
| 651 | (VOID *)&S3MSRPreSelfRefKB, |
| 652 | NULL, |
| 653 | NULL, |
| 654 | NULL |
| 655 | }; |
| 656 | |
| 657 | /*---------------------------------------------------------------------------- |
| 658 | * EXPORTED FUNCTIONS |
| 659 | * |
| 660 | *---------------------------------------------------------------------------- |
| 661 | */ |
| 662 | /* -----------------------------------------------------------------------------*/ |
| 663 | /** |
| 664 | * |
| 665 | * |
| 666 | * This function initializes the northbridge block for S3 resume |
| 667 | * |
| 668 | * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. |
| 669 | * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. |
| 670 | * @param[in] NodeID - Node ID of the target node. |
| 671 | * |
| 672 | * @return BOOLEAN |
| 673 | * TRUE - This is the correct constructor for the targeted node. |
| 674 | * FALSE - This isn't the correct constructor for the targeted node. |
| 675 | */ |
| 676 | BOOLEAN |
| 677 | MemS3ResumeConstructNBBlockKB ( |
| 678 | IN OUT VOID *S3NBPtr, |
| 679 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 680 | IN UINT8 NodeID |
| 681 | ) |
| 682 | { |
| 683 | INT32 i; |
| 684 | MEM_NB_BLOCK *NBPtr; |
| 685 | |
| 686 | NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; |
| 687 | |
| 688 | // |
| 689 | // Determine if this is the expected NB Type |
| 690 | // |
| 691 | GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); |
| 692 | if (!MemNIsIdSupportedKB (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { |
| 693 | return FALSE; |
| 694 | } |
| 695 | |
| 696 | NBPtr->RefPtr = NULL; |
| 697 | NBPtr->MemPtr = MemPtr; |
| 698 | NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); |
| 699 | NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; |
| 700 | MemNInitNBRegTableKB (NBPtr, NBPtr->NBRegTable); |
| 701 | NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; |
| 702 | NBPtr->Dct = 0; |
| 703 | NBPtr->Channel = 0; |
| 704 | NBPtr->Ganged = FALSE; |
| 705 | NBPtr->NodeCount = MAX_NODES_SUPPORTED_KB; |
| 706 | NBPtr->DctCount = MAX_DCTS_PER_NODE_KB; |
| 707 | NBPtr->MemPstate = MEMORY_PSTATE0; |
| 708 | NBPtr->MemPstateStage = 0; |
| 709 | NBPtr->NbPsCtlReg = 0; |
| 710 | |
| 711 | NBPtr->IsSupported[SetDllShutDown] = TRUE; |
| 712 | |
| 713 | for (i = 0; i < EnumSize; i++) { |
| 714 | NBPtr->IsSupported[i] = FALSE; |
| 715 | } |
| 716 | |
| 717 | for (i = 0; i < NumberOfHooks; i++) { |
| 718 | NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; |
| 719 | } |
| 720 | |
| 721 | LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); |
| 722 | |
| 723 | NBPtr->SwitchDCT = MemNSwitchDCTNb; |
| 724 | NBPtr->SwitchChannel = MemNSwitchChannelNb; |
| 725 | NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldKB; |
| 726 | NBPtr->GetBitField = MemNGetBitFieldNb; |
| 727 | NBPtr->SetBitField = MemNSetBitFieldNb; |
| 728 | NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedKB; |
| 729 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet; |
| 730 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskKB; |
| 731 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; |
| 732 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeUNb; |
| 733 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; |
| 734 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrKB; |
| 735 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstKB; |
| 736 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0; |
| 737 | NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNS3DctCfgSelectUnb; |
| 738 | |
| 739 | MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0); |
| 740 | MemNSwitchDCTNb (NBPtr, 0); |
| 741 | MemNSetBitFieldNb (NBPtr, BFMemPsSel, 0); |
| 742 | |
| 743 | if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) != 1) { |
| 744 | NBPtr->MemPstateStage = MEMORY_PSTATE_S3_STAGE; |
| 745 | MemNBrdcstSetUnConditionalNb (NBPtr, BFPStateToAccess, 0); |
| 746 | } |
| 747 | |
| 748 | return TRUE; |
| 749 | } |
| 750 | |
| 751 | /*---------------------------------------------------------------------------- |
| 752 | * LOCAL FUNCTIONS |
| 753 | * |
| 754 | *----------------------------------------------------------------------------*/ |
| 755 | |
| 756 | /* -----------------------------------------------------------------------------*/ |
| 757 | /** |
| 758 | * |
| 759 | * |
| 760 | * This function returns the register list for each device for KB |
| 761 | * |
| 762 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 763 | * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP |
| 764 | * @return UINT16 - size of the device descriptor on the target node. |
| 765 | */ |
| 766 | UINT16 |
| 767 | STATIC |
| 768 | MemNS3GetRegLstPtrKB ( |
| 769 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 770 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 771 | ) |
| 772 | { |
| 773 | UINT8 i; |
| 774 | UINT16 Size; |
| 775 | Size = 0; |
| 776 | for (i = PRESELFREF; i <= POSTSELFREF; i ++) { |
| 777 | DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); |
| 778 | DescriptPtr->PCIDevice[i].Node = NBPtr->Node; |
| 779 | DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; |
| 780 | if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListKB[PCI_LST_ESR_KB - PCI_LST_ESR_KB + i] != NULL) { |
| 781 | DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_KB + i; |
| 782 | Size += sizeof (PCI_DEVICE_DESCRIPTOR); |
| 783 | } |
| 784 | DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); |
| 785 | DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; |
| 786 | DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; |
| 787 | if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListKB[CPCI_LST_ESR_KB - PCI_LST_ESR_KB + i] != NULL) { |
| 788 | DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_KB + i; |
| 789 | Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); |
| 790 | } |
| 791 | DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); |
| 792 | DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; |
| 793 | if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListKB[MSR_LST_ESR_KB - PCI_LST_ESR_KB + i] != NULL) { |
| 794 | DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_KB + i; |
| 795 | Size += sizeof (MSR_DEVICE_DESCRIPTOR); |
| 796 | } |
| 797 | DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); |
| 798 | DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; |
| 799 | if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListKB[CMSR_LST_ESR_KB - PCI_LST_ESR_KB + i] != NULL) { |
| 800 | DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_KB + i; |
| 801 | Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); |
| 802 | } |
| 803 | } |
| 804 | return Size; |
| 805 | } |
| 806 | |
| 807 | /* -----------------------------------------------------------------------------*/ |
| 808 | /** |
| 809 | * |
| 810 | * |
| 811 | * This function return the register list according to the register ID. |
| 812 | * |
| 813 | * @param[in] RegisterLstID - value of the Register list ID. |
| 814 | * @param[out] **RegisterHeader - pointer to the address of the register list. |
| 815 | * @return AGESA_STATUS |
| 816 | * - AGESA_FATAL |
| 817 | * - AGESA_SUCCESS |
| 818 | */ |
| 819 | AGESA_STATUS |
| 820 | STATIC |
| 821 | MemNS3GetDeviceRegLstKB ( |
| 822 | IN UINT32 RegisterLstID, |
| 823 | OUT VOID **RegisterHeader |
| 824 | ) |
| 825 | { |
| 826 | if (RegisterLstID >= (sizeof (MemS3RegListKB) / sizeof (VOID *))) { |
| 827 | ASSERT(FALSE); // RegisterListID exceeded size of Register list |
| 828 | return AGESA_FATAL; |
| 829 | } |
| 830 | if (MemS3RegListKB[RegisterLstID] != NULL) { |
| 831 | *RegisterHeader = MemS3RegListKB[RegisterLstID]; |
| 832 | return AGESA_SUCCESS; |
| 833 | } |
| 834 | ASSERT(FALSE); // Device register list error |
| 835 | return AGESA_FATAL; |
| 836 | } |
| 837 | |
| 838 | /* -----------------------------------------------------------------------------*/ |
| 839 | /** |
| 840 | * |
| 841 | * |
| 842 | * This function that set PllLockTime or disable auto compensation. |
| 843 | * |
| 844 | * @param[in] AccessWidth - Access width of the register. |
| 845 | * @param[in] Address - address in PCI_ADDR format. |
| 846 | * @param[in, out] *Value - Pointer to the value to be written. |
| 847 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 848 | * @return none |
| 849 | */ |
| 850 | VOID |
| 851 | STATIC |
| 852 | MemNS3SetDfltPhyRegKB ( |
| 853 | IN ACCESS_WIDTH AccessWidth, |
| 854 | IN PCI_ADDR Address, |
| 855 | IN VOID *Value, |
| 856 | IN OUT VOID *ConfigPtr |
| 857 | ) |
| 858 | { |
| 859 | UINT16 RegValue; |
| 860 | BIT_FIELD_NAME BitField; |
| 861 | |
| 862 | IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { |
| 863 | BitField = (BIT_FIELD_NAME) Address.Address.Register; |
| 864 | RegValue = 0; |
| 865 | |
| 866 | if (BitField == BFPllLockTime) { |
| 867 | RegValue = 0x190; |
| 868 | } else if (BitField == BFDisablePredriverCal) { |
| 869 | RegValue = 3; |
| 870 | } else { |
| 871 | ASSERT (FALSE); |
| 872 | } |
| 873 | MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); |
| 874 | } |
| 875 | } |
| 876 | |
| 877 | /* -----------------------------------------------------------------------------*/ |
| 878 | /** |
| 879 | * |
| 880 | * |
| 881 | * This function sets bit 31 [DynModeChange] of F2x9C_xB |
| 882 | * |
| 883 | * @param[in] AccessWidth - Access width of the register. |
| 884 | * @param[in] Address - address in PCI_ADDR format. |
| 885 | * @param[in, out] *Value - Pointer to the value to be written. |
| 886 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 887 | * @return none |
| 888 | */ |
| 889 | VOID |
| 890 | STATIC |
| 891 | MemNS3SetDynModeChangeKB ( |
| 892 | IN ACCESS_WIDTH AccessWidth, |
| 893 | IN PCI_ADDR Address, |
| 894 | IN OUT VOID *Value, |
| 895 | IN OUT VOID *ConfigPtr |
| 896 | ) |
| 897 | { |
| 898 | UINT32 RegValue; |
| 899 | |
| 900 | IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { |
| 901 | if ((Address.Address.Register & 0x400) == 0) { |
| 902 | RegValue = 0x40000000; |
| 903 | MemNS3SetCSRKB (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); |
| 904 | } |
| 905 | RegValue = 0x80000000; |
| 906 | MemNS3SetCSRKB (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); |
| 907 | } |
| 908 | } |
| 909 | |
| 910 | /* -----------------------------------------------------------------------------*/ |
| 911 | /** |
| 912 | * |
| 913 | * |
| 914 | * This function sets F2x9C_xB to 0x80800000 |
| 915 | * |
| 916 | * @param[in] AccessWidth - Access width of the register. |
| 917 | * @param[in] Address - address in PCI_ADDR format. |
| 918 | * @param[in, out] *Value - Pointer to the value to be written. |
| 919 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 920 | * @return none |
| 921 | */ |
| 922 | VOID |
| 923 | STATIC |
| 924 | MemNS3SetPhyStatusRegKB ( |
| 925 | IN ACCESS_WIDTH AccessWidth, |
| 926 | IN PCI_ADDR Address, |
| 927 | IN OUT VOID *Value, |
| 928 | IN OUT VOID *ConfigPtr |
| 929 | ) |
| 930 | { |
| 931 | UINT32 RegValue; |
| 932 | |
| 933 | IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { |
| 934 | RegValue = 0x80800000; |
| 935 | MemNS3SetCSRKB (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); |
| 936 | } |
| 937 | } |
| 938 | |
| 939 | /* -----------------------------------------------------------------------------*/ |
| 940 | /** |
| 941 | * |
| 942 | * |
| 943 | * This function does the channel disable sequence |
| 944 | * |
| 945 | * @param[in] AccessWidth - Access width of the register. |
| 946 | * @param[in] Address - address in PCI_ADDR format. |
| 947 | * @param[in, out] *Value - Pointer to the value to be written. |
| 948 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 949 | * @return none |
| 950 | */ |
| 951 | VOID |
| 952 | STATIC |
| 953 | MemNS3DisableChannelKB ( |
| 954 | IN ACCESS_WIDTH AccessWidth, |
| 955 | IN PCI_ADDR Address, |
| 956 | IN OUT VOID *Value, |
| 957 | IN OUT VOID *ConfigPtr |
| 958 | ) |
| 959 | { |
| 960 | MEM_NB_BLOCK *NBPtr; |
| 961 | LOCATE_HEAP_PTR LocateBufferPtr; |
| 962 | S3_MEM_NB_BLOCK *S3NBPtr; |
| 963 | UINT32 RegValue; |
| 964 | UINT8 Die; |
| 965 | |
| 966 | // See which Node should be accessed |
| 967 | Die = (UINT8) (Address.Address.Device - 24); |
| 968 | |
| 969 | LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; |
| 970 | if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { |
| 971 | S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; |
| 972 | NBPtr = S3NBPtr[Die].NBPtr; |
| 973 | |
| 974 | // Function field contains the DCT number |
| 975 | NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); |
| 976 | RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri); |
| 977 | // if CKETri is 0b1111, this channel is disabled |
| 978 | if (RegValue == 0xF) { |
| 979 | //Wait for 24 MEMCLKs, which is 60ns under 400MHz |
| 980 | MemFS3Wait10ns (6, NBPtr->MemPtr); |
| 981 | MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); |
| 982 | MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); |
| 983 | } |
| 984 | } |
| 985 | } |
| 986 | |
| 987 | /* -----------------------------------------------------------------------------*/ |
| 988 | /** |
| 989 | * |
| 990 | * |
| 991 | * This function changes memory Pstate context |
| 992 | * |
| 993 | * @param[in] AccessWidth - Access width of the register. |
| 994 | * @param[in] Address - address in PCI_ADDR format. |
| 995 | * @param[in, out] *Value - Pointer to the value to be written. |
| 996 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 997 | * |
| 998 | * @return TRUE |
| 999 | * ---------------------------------------------------------------------------- |
| 1000 | */ |
| 1001 | VOID |
| 1002 | STATIC |
| 1003 | MemNS3ChangeMemPStateContextAndFlowNb ( |
| 1004 | IN ACCESS_WIDTH AccessWidth, |
| 1005 | IN PCI_ADDR Address, |
| 1006 | IN OUT VOID *Value, |
| 1007 | IN OUT VOID *ConfigPtr |
| 1008 | ) |
| 1009 | { |
| 1010 | MEM_NB_BLOCK *NBPtr; |
| 1011 | LOCATE_HEAP_PTR LocateBufferPtr; |
| 1012 | S3_MEM_NB_BLOCK *S3NBPtr; |
| 1013 | UINT8 Die; |
| 1014 | |
| 1015 | // See which Node should be accessed |
| 1016 | Die = (UINT8) (Address.Address.Device - 24); |
| 1017 | |
| 1018 | LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; |
| 1019 | |
| 1020 | if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { |
| 1021 | S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; |
| 1022 | NBPtr = S3NBPtr[Die].NBPtr; |
| 1023 | if (NBPtr->MemPstate == MEMORY_PSTATE0) { |
| 1024 | // If MemoryPstate is not disabled, switch to MemPState 1 context, and reprocess the register list |
| 1025 | MemNChangeMemPStateContextNb (NBPtr, 1); |
| 1026 | *(UINT32 *) Value = RESTART_FROM_BEGINNING_LIST; |
| 1027 | } else { |
| 1028 | // Switch back to MemPstate0 Context |
| 1029 | MemNChangeMemPStateContextNb (NBPtr, 0); |
| 1030 | } |
| 1031 | } |
| 1032 | } |
| 1033 | |
| 1034 | /* -----------------------------------------------------------------------------*/ |
| 1035 | /** |
| 1036 | * |
| 1037 | * |
| 1038 | * This function returns the conditional PCI device mask |
| 1039 | * |
| 1040 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 1041 | * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP |
| 1042 | * @return none |
| 1043 | */ |
| 1044 | VOID |
| 1045 | STATIC |
| 1046 | MemNS3GetConPCIMaskKB ( |
| 1047 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1048 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 1049 | ) |
| 1050 | { |
| 1051 | BIT_FIELD_NAME bitfield; |
| 1052 | UINT32 RegVal; |
| 1053 | UINT8 DCT; |
| 1054 | UINT8 DimmMask; |
| 1055 | UINT8 BadDimmMask; |
| 1056 | UINT8 NbPsCapMsk; |
| 1057 | UINT8 MemPstateMsk; |
| 1058 | UINT8 CsPerDelay; |
| 1059 | |
| 1060 | NbPsCapMsk = 0; |
| 1061 | MemPstateMsk = 0; |
| 1062 | DimmMask = 0; |
| 1063 | BadDimmMask = 0; |
| 1064 | CsPerDelay = 1; |
| 1065 | |
| 1066 | for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { |
| 1067 | MemNSwitchDCTNb (NBPtr, DCT); |
| 1068 | if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { |
| 1069 | if (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn) == 0) { |
| 1070 | CsPerDelay = 2; |
| 1071 | } |
| 1072 | for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { |
| 1073 | RegVal = MemNGetBitFieldNb (NBPtr, bitfield); |
| 1074 | if (RegVal & 0x1) { |
| 1075 | DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) / CsPerDelay) << 1) + DCT)); |
| 1076 | } else if (RegVal & 0x4) { |
| 1077 | BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) / CsPerDelay) << 1) + DCT)); |
| 1078 | } |
| 1079 | } |
| 1080 | } |
| 1081 | } |
| 1082 | // Check if the system is capable of doing NB Pstate change |
| 1083 | if (MemNGetBitFieldNb (NBPtr, BFNbPstateDis) == 0) { |
| 1084 | NbPsCapMsk = DCT0_NBPSTATE_SUPPORT_MASK; |
| 1085 | } |
| 1086 | if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) == 0) { |
| 1087 | MemPstateMsk = DCT0_MEMPSTATE_MASK; |
| 1088 | } |
| 1089 | |
| 1090 | MemNSwitchDCTNb (NBPtr, 0); |
| 1091 | // Set channel mask |
| 1092 | DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; |
| 1093 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; |
| 1094 | for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { |
| 1095 | if (DimmMask & (0x55 << DCT)) { |
| 1096 | // Set mask before exit self refresh |
| 1097 | DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (NbPsCapMsk | MemPstateMsk | 1) << DCT; |
| 1098 | // Set mask after exit self refresh |
| 1099 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (NbPsCapMsk | MemPstateMsk | 1) << DCT; |
| 1100 | } else if (BadDimmMask & (0x55 << DCT)) { |
| 1101 | // Need to save function 2 registers for bad dimm |
| 1102 | DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; |
| 1103 | } |
| 1104 | } |
| 1105 | |
| 1106 | // Set dimm mask |
| 1107 | DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; |
| 1108 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; |
| 1109 | } |
| 1110 | |
| 1111 | /* -----------------------------------------------------------------------------*/ |
| 1112 | /** |
| 1113 | * |
| 1114 | * |
| 1115 | * This function read the value of CSR register. |
| 1116 | * |
| 1117 | * @param[in] AccessWidth - Access width of the register |
| 1118 | * @param[in] Address - address of the CSR register in PCI_ADDR format. |
| 1119 | * @param[in] *Value - Pointer to the value be read. |
| 1120 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1121 | * @return none |
| 1122 | */ |
| 1123 | VOID |
| 1124 | STATIC |
| 1125 | MemNS3GetCSRKB ( |
| 1126 | IN ACCESS_WIDTH AccessWidth, |
| 1127 | IN PCI_ADDR Address, |
| 1128 | IN VOID *Value, |
| 1129 | IN OUT VOID *ConfigPtr |
| 1130 | ) |
| 1131 | { |
| 1132 | UINT8 TempValue; |
| 1133 | UINT8 Dct; |
| 1134 | UINT32 ExtendOffset; |
| 1135 | UINT32 TempFunc; |
| 1136 | |
| 1137 | ExtendOffset = Address.Address.Register; |
| 1138 | TempFunc = Address.Address.Function; |
| 1139 | |
| 1140 | // Switch Dct |
| 1141 | Address.Address.Function = FUNC_1; |
| 1142 | Address.Address.Register = 0x10C; |
| 1143 | Dct = 0; |
| 1144 | if (ExtendOffset & 0x400) { |
| 1145 | Dct = 1; |
| 1146 | } |
| 1147 | LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); |
| 1148 | TempValue = (TempValue & 0xF8) | Dct; |
| 1149 | LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); |
| 1150 | Address.Address.Function = TempFunc; |
| 1151 | |
| 1152 | Address.Address.Register = 0x98; |
| 1153 | ExtendOffset &= 0x3FF; |
| 1154 | LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); |
| 1155 | IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr); |
| 1156 | Address.Address.Register = 0x9C; |
| 1157 | LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); |
| 1158 | } |
| 1159 | |
| 1160 | /* -----------------------------------------------------------------------------*/ |
| 1161 | /** |
| 1162 | * |
| 1163 | * |
| 1164 | * This function write to a CSR register |
| 1165 | * |
| 1166 | * @param[in] AccessWidth - Access width of the register |
| 1167 | * @param[in] Address - address of the CSR register in PCI_ADDR format. |
| 1168 | * @param[in, out] *Value - Pointer to the value be read. |
| 1169 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1170 | * @return none |
| 1171 | */ |
| 1172 | VOID |
| 1173 | STATIC |
| 1174 | MemNS3SetCSRKB ( |
| 1175 | IN ACCESS_WIDTH AccessWidth, |
| 1176 | IN PCI_ADDR Address, |
| 1177 | IN OUT VOID *Value, |
| 1178 | IN OUT VOID *ConfigPtr |
| 1179 | ) |
| 1180 | { |
| 1181 | UINT8 TempValue; |
| 1182 | UINT8 Dct; |
| 1183 | UINT32 ExtendOffset; |
| 1184 | UINT32 ValueWrite; |
| 1185 | UINT32 TempFunc; |
| 1186 | |
| 1187 | ExtendOffset = Address.Address.Register; |
| 1188 | |
| 1189 | TempFunc = Address.Address.Function; |
| 1190 | // Switch Dct |
| 1191 | Address.Address.Function = FUNC_1; |
| 1192 | Address.Address.Register = 0x10C; |
| 1193 | Dct = 0; |
| 1194 | if (ExtendOffset & 0x400) { |
| 1195 | Dct = 1; |
| 1196 | } |
| 1197 | LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); |
| 1198 | TempValue = (TempValue & 0xFE) | Dct; |
| 1199 | LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); |
| 1200 | |
| 1201 | Address.Address.Function = TempFunc; |
| 1202 | Address.Address.Register = 0x9C; |
| 1203 | |
| 1204 | ExtendOffset &= 0x3FF; |
| 1205 | ExtendOffset |= 0x40000000; |
| 1206 | switch (AccessWidth) { |
| 1207 | case AccessS3SaveWidth8: |
| 1208 | ValueWrite = *(UINT8 *) Value; |
| 1209 | break; |
| 1210 | case AccessS3SaveWidth16: |
| 1211 | ValueWrite = *(UINT16 *) Value; |
| 1212 | break; |
| 1213 | case AccessS3SaveWidth32: |
| 1214 | ValueWrite = *(UINT32 *) Value; |
| 1215 | break; |
| 1216 | default: |
| 1217 | ASSERT (FALSE); |
| 1218 | } |
| 1219 | LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr); |
| 1220 | Address.Address.Register = 0x98; |
| 1221 | LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); |
| 1222 | IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr); |
| 1223 | } |
| 1224 | |
| 1225 | /* -----------------------------------------------------------------------------*/ |
| 1226 | /** |
| 1227 | * |
| 1228 | * |
| 1229 | * This function that set Phy Fence |
| 1230 | * |
| 1231 | * @param[in] AccessWidth - Access width of the register. |
| 1232 | * @param[in] Address - address in PCI_ADDR format. |
| 1233 | * @param[in, out] *Value - Pointer to the value to be written. |
| 1234 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1235 | * @return none |
| 1236 | */ |
| 1237 | VOID |
| 1238 | STATIC |
| 1239 | MemNS3SetPhyFenceKB ( |
| 1240 | IN ACCESS_WIDTH AccessWidth, |
| 1241 | IN PCI_ADDR Address, |
| 1242 | IN VOID *Value, |
| 1243 | IN OUT VOID *ConfigPtr |
| 1244 | ) |
| 1245 | { |
| 1246 | UINT16 FenceValue; |
| 1247 | UINT16 Fence2Data; |
| 1248 | UINT16 Fence2Reg; |
| 1249 | BIT_FIELD_NAME BitField; |
| 1250 | MEM_NB_BLOCK *NBPtr; |
| 1251 | LOCATE_HEAP_PTR LocateBufferPtr; |
| 1252 | S3_MEM_NB_BLOCK *S3NBPtr; |
| 1253 | |
| 1254 | BitField = (BIT_FIELD_NAME) Address.Address.Register; |
| 1255 | FenceValue = *(UINT16 *) Value; |
| 1256 | // See which Node should be accessed |
| 1257 | |
| 1258 | LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; |
| 1259 | |
| 1260 | if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { |
| 1261 | S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; |
| 1262 | NBPtr = S3NBPtr[0].NBPtr; |
| 1263 | |
| 1264 | // Do nothing if currently in memory pstate 0 context |
| 1265 | if (NBPtr->MemPstate == MEMORY_PSTATE0) { |
| 1266 | return; |
| 1267 | } |
| 1268 | |
| 1269 | MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 16, BFPhyFence); |
| 1270 | MemNSetBitFieldNb (NBPtr, BFPhyFence, FenceValue); |
| 1271 | |
| 1272 | // Program Fence 2 for MState 1 |
| 1273 | Fence2Data = 0; |
| 1274 | if ((FenceValue & 0x1F) < 16) { |
| 1275 | Fence2Data |= (FenceValue & 0x1F) | 0x10; |
| 1276 | } |
| 1277 | if (((FenceValue >> 5) & 0x1F) < 16) { |
| 1278 | Fence2Data |= (((FenceValue >> 5) & 0x1F) | 0x10) << 10; |
| 1279 | } |
| 1280 | if (((FenceValue >> 10) & 0x1F) < 16) { |
| 1281 | Fence2Data |= (((FenceValue >> 10) & 0x1F) | 0x10) << 5; |
| 1282 | } |
| 1283 | MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data); |
| 1284 | |
| 1285 | // Program another Fence 2 register for Mstate 1 |
| 1286 | Fence2Reg = (UINT16) MemNGetBitFieldNb (NBPtr, BFFence2); |
| 1287 | Fence2Reg = (Fence2Reg &~(UINT16) ((0x1F << 10) | 0x1F)) | (Fence2Data & 0x1F) | (((Fence2Data >> 5) & 0x1F) << 10); |
| 1288 | MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Reg); |
| 1289 | } |
| 1290 | } |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 1291 | |
| 1292 | /* -----------------------------------------------------------------------------*/ |
| 1293 | /** |
| 1294 | * |
| 1295 | * |
| 1296 | * This function sets MemClkFreqVal bit, adding an intermediate frequency hop |
| 1297 | * to 333Mhz before changing to the target DDR rate. This sequence is |
| 1298 | * intended to mimic the initial boot frequency ramp. |
| 1299 | * |
| 1300 | * @param[in] AccessWidth - Access width of the register. |
| 1301 | * @param[in] Address - address in PCI_ADDR format. |
| 1302 | * @param[in, out] *Value - Pointer to the value to be written. |
| 1303 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1304 | * @return none |
| 1305 | */ |
| 1306 | VOID |
| 1307 | MemNS3SetMemClkFreqValKB ( |
| 1308 | IN ACCESS_WIDTH AccessWidth, |
| 1309 | IN PCI_ADDR Address, |
| 1310 | IN OUT VOID *Value, |
| 1311 | IN OUT VOID *ConfigPtr |
| 1312 | ) |
| 1313 | { |
| 1314 | UINT32 TempValue; |
| 1315 | UINT32 TempMemClk; |
| 1316 | |
| 1317 | // 1. Save the current MemClkFreq |
| 1318 | MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); |
| 1319 | TempMemClk = TempValue; |
| 1320 | |
| 1321 | // 2. Program MemClkFreq = 200MHz, MemClkFreqVal = 1; |
| 1322 | TempValue &= 0xFFFFFF00; |
| 1323 | TempValue |= 0x82; |
| 1324 | MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); |
| 1325 | |
| 1326 | // 3. Wait for FreqChgInPrg == 0 |
| 1327 | MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); |
| 1328 | while ((TempValue & 0x200000) != 0) { |
| 1329 | MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); |
| 1330 | } |
| 1331 | |
| 1332 | // 4. Program MemClkFreqVal = 0, Restore MemClkFreq |
| 1333 | TempValue &= 0xFFFFFFEF; |
| 1334 | MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempMemClk, ConfigPtr); |
| 1335 | |
| 1336 | // 5. Program MemClkFreqVal = 1 |
| 1337 | MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); |
| 1338 | TempValue |= 0x80; |
| 1339 | MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); |
| 1340 | |
| 1341 | // 6. Wait for FreqChgInPrg = 0 |
| 1342 | MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); |
| 1343 | while ((TempValue & 0x200000) != 0) { |
| 1344 | MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); |
| 1345 | } |
| 1346 | } |