Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * NB services |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 85506 $ @e \$Date: 2013-01-08 15:38:33 -0600 (Tue, 08 Jan 2013) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "amdlib.h" |
| 53 | #include "S3SaveState.h" |
| 54 | #include "Gnb.h" |
| 55 | #include "GnbPcieConfig.h" |
| 56 | #include "GnbCommonLib.h" |
| 57 | #include "GnbPcieInitLibV1.h" |
| 58 | #include "GnbSmuInitLibV7.h" |
| 59 | #include "heapManager.h" |
| 60 | #include "GnbFamServices.h" |
| 61 | #include "Filecode.h" |
| 62 | #define FILECODE PROC_GNB_MODULES_GNBSMULIBV7_GNBSMUINITLIBV7_FILECODE |
| 63 | /*---------------------------------------------------------------------------------------- |
| 64 | * D E F I N I T I O N S A N D M A C R O S |
| 65 | *---------------------------------------------------------------------------------------- |
| 66 | */ |
| 67 | |
| 68 | #define SMC_RAM_START_ADDR 0x20000ul |
| 69 | #ifndef INVALID_SMU_MSG |
| 70 | #define INVALID_SMU_MSG 0xFF |
| 71 | #endif |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * T Y P E D E F S A N D S T R U C T U R E S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | /*---------------------------------------------------------------------------------------- |
| 79 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 80 | *---------------------------------------------------------------------------------------- |
| 81 | */ |
| 82 | VOID |
| 83 | GnbSmuServiceRequestV7S3Script ( |
| 84 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 85 | IN UINT16 ContextLength, |
| 86 | IN VOID *Context |
| 87 | ); |
| 88 | |
| 89 | /*----------------------------------------------------------------------------------------*/ |
| 90 | /** |
| 91 | * SMU service request |
| 92 | * |
| 93 | * |
| 94 | * @param[in] DevObject Pointer to Device object |
| 95 | * @param[in] RequestId Request ID |
| 96 | * @param[in] RequestArgument Request Argument |
| 97 | * @param[in] AccessFlags See GNB_ACCESS_FLAGS_* definitions |
| 98 | */ |
| 99 | |
| 100 | VOID |
| 101 | GnbSmuServiceRequestV7 ( |
| 102 | IN DEV_OBJECT *DevObject, |
| 103 | IN UINT8 RequestId, |
| 104 | IN UINT32 RequestArgument, |
| 105 | IN UINT32 AccessFlags |
| 106 | ) |
| 107 | { |
| 108 | UINT32 BFIntDone; |
| 109 | UINT32 BFIntToggle; |
| 110 | UINT32 BFIntAck; |
| 111 | UINT32 RxSmuIntArgument; |
| 112 | URA_TUPLE UraTuple[2]; |
| 113 | UINT32 IsMsgValid; |
| 114 | |
| 115 | IsMsgValid = FALSE; |
| 116 | if (RequestId != INVALID_SMU_MSG) { |
| 117 | IsMsgValid = TRUE; |
| 118 | } |
| 119 | |
| 120 | if (IsMsgValid == TRUE) { |
| 121 | IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV7 Enter\n"); |
| 122 | IDS_HDT_CONSOLE (NB_MISC, " Service Request %d\n", RequestId); |
| 123 | IDS_HDT_CONSOLE (NB_MISC, " Service Request Argument 0x%x\n", RequestArgument); |
| 124 | |
| 125 | if ((AccessFlags & GNB_REG_ACC_FLAG_S3SAVE) != 0) { |
| 126 | SMU_MSG_CONTEXTV7 SmuMsgContext; |
| 127 | SmuMsgContext.GnbPciAddress.AddressValue = DevObject->DevPciAddress.AddressValue; |
| 128 | SmuMsgContext.RequestId = RequestId; |
| 129 | SmuMsgContext.RequestArgument = RequestArgument; |
| 130 | S3_SAVE_DISPATCH (DevObject->StdHeader, GnbSmuServiceRequestV7S3Script_ID, sizeof (SmuMsgContext), &SmuMsgContext); |
| 131 | } |
| 132 | |
| 133 | do { |
| 134 | GnbUraGet (DevObject, TBfxSmuIntDone, &BFIntDone); |
| 135 | } while (BFIntDone == 0x0); |
| 136 | |
| 137 | RxSmuIntArgument = RequestArgument; |
| 138 | GnbUraSet (DevObject, TRxSmuIntArgument, &RxSmuIntArgument); |
| 139 | |
| 140 | GnbUraGet (DevObject, TBfxSmuIntToggle, &BFIntToggle); |
| 141 | UraTuple[0].Token = TBfxSmuIntToggle; |
| 142 | UraTuple[0].Value = ~BFIntToggle; |
| 143 | UraTuple[1].Token = TBfxSmuServiceIndex; |
| 144 | UraTuple[1].Value = RequestId; |
| 145 | GnbUraCombinedSet (DevObject, TRxSmuIntReq, &UraTuple[0], 2); |
| 146 | |
| 147 | do { |
| 148 | GnbUraGet (DevObject, TBfxSmuIntAck, &BFIntAck); |
| 149 | } while (BFIntAck == 0x0); |
| 150 | |
| 151 | do { |
| 152 | GnbUraGet (DevObject, TBfxSmuIntDone, &BFIntDone); |
| 153 | } while (BFIntDone == 0x0); |
| 154 | |
| 155 | IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV7 Exit\n"); |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | /*----------------------------------------------------------------------------------------*/ |
| 160 | /** |
| 161 | * SMU service request for S3 script |
| 162 | * |
| 163 | * |
| 164 | * @param[in] StdHeader Standard configuration header |
| 165 | * @param[in] ContextLength Context length |
| 166 | * @param[in] Context Pointer to Context |
| 167 | */ |
| 168 | |
| 169 | VOID |
| 170 | GnbSmuServiceRequestV7S3Script ( |
| 171 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 172 | IN UINT16 ContextLength, |
| 173 | IN VOID *Context |
| 174 | ) |
| 175 | { |
| 176 | SMU_MSG_CONTEXTV7 *SmuMsgContext; |
| 177 | DEV_OBJECT DevObject; |
| 178 | SmuMsgContext = (SMU_MSG_CONTEXTV7 *) Context; |
| 179 | |
| 180 | DevObject.StdHeader = StdHeader; |
| 181 | DevObject.DevPciAddress = SmuMsgContext->GnbPciAddress; |
| 182 | DevObject.GnbHandle = GnbGetHandle (StdHeader); |
| 183 | |
| 184 | GnbSmuServiceRequestV7 (&DevObject, SmuMsgContext->RequestId, SmuMsgContext->RequestArgument, 0); |
| 185 | } |
| 186 | |
| 187 | /*----------------------------------------------------------------------------------------*/ |
| 188 | /** |
| 189 | * SMU firmware download |
| 190 | * |
| 191 | * |
| 192 | * @param[in] GnbHandle Pointer to GNB_HANDLE |
| 193 | * @param[in] Firmware Pointer t0 firmware |
| 194 | * @param[in] StdHeader Standard configuration header |
| 195 | */ |
| 196 | |
| 197 | AGESA_STATUS |
| 198 | GnbSmuFirmwareLoadV7 ( |
| 199 | IN GNB_HANDLE *GnbHandle, |
| 200 | IN FIRMWARE_HEADER_V7 *Firmware, |
| 201 | IN AMD_CONFIG_PARAMS *StdHeader |
| 202 | ) |
| 203 | { |
| 204 | AGESA_STATUS Status; |
| 205 | UINT32 BfxSmuProtectedMode; |
| 206 | UINT32 BfxSmuBootSeqDone; |
| 207 | UINT32 BfxSmuAuthDone; |
| 208 | UINT32 BfxSmuAuthPass; |
| 209 | UINT32 RxSmuAuthVector; |
| 210 | UINT32 BfxSmuRstReg; |
| 211 | UINT32 BfxSmuCkDisable; |
| 212 | UINT32 BfxSmuInterruptsEnabled; |
| 213 | UINT32 RxSmuRamStartAddr; |
| 214 | GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol; |
| 215 | PCI_ADDR GnbPciAddress; |
| 216 | DEV_OBJECT DevObject; |
| 217 | URA_TUPLE UraTuple; |
| 218 | |
| 219 | IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV7 Enter\n"); |
| 220 | IDS_HDT_CONSOLE (NB_MISC, " Firmware version 0x%x\n", Firmware->Version); |
| 221 | IDS_OPTION_HOOK (IDS_REPORT_SMU_FW_VERSION, &(Firmware->Version), StdHeader); |
| 222 | |
| 223 | GnbPciAddress = GnbGetHostPciAddress (GnbHandle); |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 224 | Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbRegisterAccessProtocol, StdHeader); |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 225 | ASSERT (Status == AGESA_SUCCESS); |
| 226 | |
| 227 | DevObject.GnbHandle = GnbHandle; |
| 228 | DevObject.StdHeader = StdHeader; |
| 229 | DevObject.DevPciAddress.AddressValue = GnbPciAddress.AddressValue; |
| 230 | |
| 231 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 2 & 10: make sure Rom firmware sequence is done\n"); |
| 232 | // Step 2, 10, make sure Rom firmware sequence is done |
| 233 | do { |
| 234 | GnbUraGet (&DevObject, TBfxSmuBootSeqDone, &BfxSmuBootSeqDone); |
| 235 | } while (BfxSmuBootSeqDone == 0); |
| 236 | |
| 237 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 1: check if firmware running in protected mode\n"); |
| 238 | // Step 1, check if firmware running in protected mode |
| 239 | GnbUraGet (&DevObject, TBfxSmuProtectedMode, &BfxSmuProtectedMode); |
| 240 | if (BfxSmuProtectedMode == 0) { |
| 241 | // Step3, Clear firmware interrupt flags |
| 242 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 3: Clear firmware interrupt flags\n"); |
| 243 | //IDS_HDT_CONSOLE (GNB_TRACE, "Read register data 0x%x\n", FIRMWARE_FLAGS.Value); |
| 244 | BfxSmuInterruptsEnabled = 0; |
| 245 | GnbUraSet (&DevObject, TBfxSmuInterruptsEnabled, &BfxSmuInterruptsEnabled); |
| 246 | } |
| 247 | |
| 248 | //Step 4, 11, Assert SMU reset |
| 249 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 4, 11: Assert SMU reset\n"); |
| 250 | BfxSmuRstReg = 1; |
| 251 | GnbUraSet (&DevObject, TBfxSmuRstReg, &BfxSmuRstReg); |
| 252 | |
| 253 | // Step5, 12, Load firmware |
| 254 | IDS_HDT_CONSOLE (GNB_TRACE, "Step5, 12, Load firmware\n"); |
| 255 | // 4 means byte length of next address during firmware download |
| 256 | UraTuple.StepLength = 4; |
| 257 | UraTuple.Value = (UINT32) ((UINTN) (Firmware)); |
| 258 | GnbUraCombinedSet (&DevObject, TRxSmuRamStartAddr | GNB_URA_STREAM_SET, &UraTuple, (Firmware->ImageSize >> 2)); |
| 259 | |
| 260 | if (BfxSmuProtectedMode == 0) { |
| 261 | IDS_HDT_CONSOLE (GNB_TRACE, "Step6, write jmp to RAM firmware\n"); |
| 262 | //Step 6, Write jmp to RAM firmware |
| 263 | RxSmuRamStartAddr = 0xE0000000 + ((SMC_RAM_START_ADDR + Firmware->HeaderSize) >> 2); |
| 264 | GnbUraSet (&DevObject, TRxSmuRomStartAddr, &RxSmuRamStartAddr); |
| 265 | } else { |
| 266 | //Step 13, Clear authentification done |
| 267 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 13, Clear authentification done\n"); |
| 268 | BfxSmuAuthDone = 0; |
| 269 | GnbUraSet (&DevObject, TBfxSmuAuthDone, &BfxSmuAuthDone); |
| 270 | } |
| 271 | |
| 272 | // Step 7, 14 Enable SMU clock |
| 273 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 7, 14 Enable SMU clock\n"); |
| 274 | BfxSmuCkDisable = 0; |
| 275 | GnbUraSet (&DevObject, TBfxSmuCkDisable, &BfxSmuCkDisable); |
| 276 | |
| 277 | //Step 8, 15, Deassert SMU reset |
| 278 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 8, 15, Deassert SMU reset\n"); |
| 279 | BfxSmuRstReg = 0; |
| 280 | GnbUraSet (&DevObject, TBfxSmuRstReg, &BfxSmuRstReg); |
| 281 | |
| 282 | if (BfxSmuProtectedMode == 1) { |
| 283 | IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init authentication vector\n"); |
| 284 | // Step 16, Wait for rom firmware init authentication vector |
| 285 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 16, Wait for rom firmware init authentication vector\n"); |
| 286 | do { |
| 287 | GnbUraGet (&DevObject, TRxSmuAuthVector, &RxSmuAuthVector); |
| 288 | } while (RxSmuAuthVector != 0x400); |
| 289 | // Call Authentication service |
| 290 | GnbSmuServiceRequestV7 (&DevObject, 0, 0, 0); |
| 291 | IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init authentication done\n"); |
| 292 | // Wait for authentication done |
| 293 | do { |
| 294 | GnbUraGet (&DevObject, TBfxSmuAuthDone, &BfxSmuAuthDone); |
| 295 | } while (BfxSmuAuthDone == 0x0); |
| 296 | |
| 297 | //Step 17, Check Authentication results |
| 298 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 17, Check Authentication results\n"); |
| 299 | GnbUraGet (&DevObject, TBfxSmuAuthPass, &BfxSmuAuthPass); |
| 300 | if (BfxSmuAuthPass == 0) { |
| 301 | IDS_HDT_CONSOLE (NB_MISC, " ERROR!!!Authentication fail!!!\n"); |
| 302 | ASSERT (FALSE); |
| 303 | return AGESA_FATAL; |
| 304 | } |
| 305 | // Step 18, Clear firmware interrupt enable flag |
| 306 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 18, Clear firmware interrupt enable flag\n"); |
| 307 | BfxSmuInterruptsEnabled = 0; |
| 308 | GnbUraSet (&DevObject, TBfxSmuInterruptsEnabled, &BfxSmuInterruptsEnabled); |
| 309 | |
| 310 | //Step 19, Assert SMU reset |
| 311 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 19, Assert SMU reset\n"); |
| 312 | BfxSmuRstReg = 1; |
| 313 | GnbUraSet (&DevObject, TBfxSmuRstReg, &BfxSmuRstReg); |
| 314 | |
| 315 | //Step 20, Deassert SMU reset |
| 316 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 20, Deassert SMU reset\n"); |
| 317 | BfxSmuRstReg = 0; |
| 318 | GnbUraSet (&DevObject, TBfxSmuRstReg, &BfxSmuRstReg); |
| 319 | } |
| 320 | |
| 321 | //Step 9, 21 Wait firmware to initialize |
| 322 | IDS_HDT_CONSOLE (GNB_TRACE, "Step 9, 21 Wait firmware to initialize\n"); |
| 323 | do { |
| 324 | GnbUraGet (&DevObject, TBfxSmuInterruptsEnabled, &BfxSmuInterruptsEnabled); |
| 325 | } while (BfxSmuInterruptsEnabled == 0); |
| 326 | |
| 327 | IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV7 Exit\n"); |
| 328 | return AGESA_SUCCESS; |
| 329 | } |