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review.coreboot.org / coreboot / b80de180c2ebd7bde5ce4da43d5e0f0c260c25e7 / . / src / vendorcode / amd / agesa / f16kb / Proc / Fch / Common / FchDef.h
blob: c1d7bb6c9380bf12971893b3c6ccb636fd55fc01 [file] [log] [blame]
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * FCH routine definition
6 *
7 *
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: FCH
12 * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
13 *
14 */
15/*
16*****************************************************************************
17*
18 * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42****************************************************************************
43*/
44#ifndef _FCH_DEF_H_
45#define _FCH_DEF_H_
46
47
48UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
49VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
50VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
51VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
52VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
53VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
54VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
Arthur Heymansb80de182022-05-16 15:29:53 +0200[diff] [blame^]55VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]56VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
57VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
58VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
59VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
Arthur Heymansb80de182022-05-16 15:29:53 +0200[diff] [blame^]60VOID ProgramFchGpioTbl (CONST IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]61VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
62VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
63BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
64VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
65VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
66VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
67VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
68VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
69VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
70VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
71VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
72VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
73VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
74UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
75
76///
77/// Fch Ab Routines
78///
79/// Pei Phase
80///
81VOID FchInitResetAb (IN VOID* FchDataPtr);
82VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
83///
84/// Dxe Phase
85///
86VOID FchInitEnvAb (IN VOID* FchDataPtr);
87VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
88VOID FchInitMidAb (IN VOID* FchDataPtr);
89VOID FchInitLateAb (IN VOID* FchDataPtr);
90///
91/// Other Public Routines
92///
93VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
94BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
95VOID FchAbLateProgram (IN VOID* FchDataPtr);
96
97///
98/// Fch Pcie Routines
99///
100/// Pei Phase
101///
102VOID FchInitResetPcie (IN VOID* FchDataPtr);
103///
104/// Dxe Phase
105///
106VOID FchInitEnvPcie (IN VOID* FchDataPtr);
107VOID FchInitMidPcie (IN VOID* FchDataPtr);
108VOID FchInitLatePcie (IN VOID* FchDataPtr);
109VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
110
111///
112/// Fch Gpp Routines
113///
114/// Pei Phase
115///
116VOID FchInitResetGpp (IN VOID* FchDataPtr);
117VOID ProgramFchGppInitReset (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
118VOID FchResetPcie (IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader);
119
120///
121/// Dxe Phase
122///
123VOID FchInitEnvGpp (IN VOID* FchDataPtr);
124VOID FchInitMidGpp (IN VOID* FchDataPtr);
125VOID FchInitLateGpp (IN VOID* FchDataPtr);
126
127///
128/// Common Gpp Routines
129///
130VOID ProgramGppTogglePcieReset (IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader);
131VOID FchGppForceGen1 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
132VOID FchGppForceGen2 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
133VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
134UINT8 GppPortPollingLtssm (IN FCH_GPP *FchGpp, IN UINT8 ActivePorts, IN BOOLEAN IsGen2, IN AMD_CONFIG_PARAMS *StdHeader);
135VOID GppGen2Workaround (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
136UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader);
137VOID FchGppPortInit (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
138VOID FchGppPortInitPhaseII (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
139VOID FchGppPortInitS3Phase (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
140UINT32 GppGetFchTempBus (IN AMD_CONFIG_PARAMS *StdHeader);
141
142///
143/// Fch Azalia Routines
144///
145/// Pei Phase
146///
147VOID FchInitResetF1 (IN VOID *FchDataPtr);
148///
149/// Dxe Phase
150///
151VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
152VOID FchInitMidAzalia (IN VOID *FchDataPtr);
153VOID FchInitLateAzalia (IN VOID *FchDataPtr);
154
155
156/// Other Public Routines
157///
158VOID FchInitGecController (IN VOID* FchDataPtr);
159VOID FchSwInitGecBootRom (IN VOID* FchDataPtr);
160
161///
162/// Fch HwAcpi Routines
163///
164/// Pei Phase
165///
166VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
167VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
168VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
169///
170/// Dxe Phase
171///
172VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
173VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
174VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
175VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
176VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
177VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
178VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
179VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
180
181///
182/// Other Public Routines
183///
184VOID HpetInit (IN VOID *FchDataPtr);
185VOID C3PopupSetting (IN VOID *FchDataPtr);
186VOID MtC1eEnable (IN VOID *FchDataPtr);
187VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
188VOID StressResetModeLate (IN VOID *FchDataPtr);
189
190///
191/// Fch Hwm Routines
192///
193/// Pei Phase
194///
195///
196/// Dxe Phase
197///
198///
199/// Other Public Routines
200///
201VOID HwmInitRegister (IN VOID* FchDataPtr);
202VOID FchECfancontrolservice (IN VOID* FchDataPtr);
203
204
205///
206/// Fch Ide Routines
207///
208VOID FchInitEnvIde (IN VOID* FchDataPtr);
209VOID FchInitMidIde (IN VOID* FchDataPtr);
210VOID FchInitLateIde (IN VOID* FchDataPtr);
211
212
213///
214/// Fch Imc Routines
215///
216/// Pei Phase
217///
218VOID FchInitResetImc (IN VOID *FchDataPtr);
219///
220/// Dxe Phase
221///
222VOID FchInitEnvImc (IN VOID *FchDataPtr);
223VOID FchInitMidImc (IN VOID *FchDataPtr);
224VOID FchInitLateImc (IN VOID *FchDataPtr);
225VOID FchInitEnvEc (IN VOID *FchDataPtr);
226VOID FchInitMidEc (IN VOID *FchDataPtr);
227VOID FchInitLateEc (IN VOID *FchDataPtr);
228///
229/// Other Public Routines
230///
231VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
232VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
233VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
234VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
235VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
236VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
237VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
238VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
239
240VOID ImcSleep (IN VOID *FchDataPtr);
241VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr);
242VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
243VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
244VOID ImcWakeup (IN VOID *FchDataPtr);
245VOID ImcIdle (IN VOID *FchDataPtr);
246BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
247VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]248VOID SoftwareDisableImc (IN VOID *FchDataPtr);
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]249
250
251///
252/// Fch Ir Routines
253///
254/// Dxe Phase
255///
256
257///
258/// Fch Pcib Routines
259///
260/// Pei Phase
261///
262VOID FchInitResetPcib (IN VOID* FchDataPtr);
263VOID FchInitResetPcibPort80Enable (IN VOID* FchDataPtr);
264
265
266
267///
268/// Fch SATA Routines
269///
270/// Pei Phase
271///
272VOID FchInitResetSata (IN VOID *FchDataPtr);
273VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
274///
275/// Dxe Phase
276///
277VOID FchInitMidSata (IN VOID *FchDataPtr);
278VOID FchInitEnvSata (IN VOID *FchDataPtr);
279VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
280VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
281VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
282
283VOID FchInitLateSata (IN VOID *FchDataPtr);
284VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
285VOID FchInitMidSataIde (IN VOID *FchDataPtr);
286VOID FchInitLateSataIde (IN VOID *FchDataPtr);
287VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
288VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
289VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
290VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
291VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
292VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
293VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
294VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
295VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
296
297VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
298VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
299VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
300VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
301VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
302VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
303VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
304VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
305VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
306VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
307VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
308VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
309VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
310VOID FchSataGpioInitial (IN VOID *FchDataPtr);
311VOID SataBar5RegSet (IN VOID *FchDataPtr);
312VOID SataSetPortGenMode (IN VOID *FchDataPtr);
313VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
314VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader);
315VOID FchSataDriveFpga (IN VOID *FchDataPtr);
316
317///
318/// FCH USB Controller Public Function
319///
320/// Pei Phase
321///
322VOID FchInitResetUsb (IN VOID *FchDataPtr);
323VOID FchInitResetOhci (IN VOID *FchDataPtr);
324VOID FchInitResetEhci (IN VOID *FchDataPtr);
325VOID FchInitResetXhci (IN VOID *FchDataPtr);
326VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
327///
328/// Dxe Phase
329///
330VOID FchInitEnvUsb (IN VOID *FchDataPtr);
331VOID FchInitMidUsb (IN VOID *FchDataPtr);
332VOID FchInitLateUsb (IN VOID *FchDataPtr);
333VOID FchInitEnvUsbOhci (IN VOID *FchDataPtr);
334VOID FchInitMidUsbOhci (IN VOID *FchDataPtr);
335VOID FchInitLateUsbOhci (IN VOID *FchDataPtr);
336VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
337VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
338VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
339VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
340VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
341VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
342VOID FchInitMidUsbOhci1 (IN VOID *FchDataPtr);
343VOID FchInitMidUsbOhci2 (IN VOID *FchDataPtr);
344VOID FchInitMidUsbOhci3 (IN VOID *FchDataPtr);
345VOID FchInitMidUsbOhci4 (IN VOID *FchDataPtr);
346VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
347VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr);
348VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr);
349///
350/// Other Public Routines
351///
352VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
353VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
354VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
355VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
356VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr);
357VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
358VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr);
WANG Siyuan7b6d4122013-07-31 16:55:26 +0800[diff] [blame]359UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr);
Siyuan Wangaffe85f2013-07-25 15:14:15 +0800[diff] [blame]360
361///
362/// Fch Sd Routines
363///
364VOID FchInitEnvSd (IN VOID *FchDataPtr);
365VOID FchInitMidSd (IN VOID *FchDataPtr);
366VOID FchInitLateSd (IN VOID *FchDataPtr);
367
368///
369/// Other Public Routines
370///
371
372VOID FchInitEnvSdProgram (IN VOID *FchDataPtr);
373
374///
375/// Fch Spi Routines
376///
377/// Pei Phase
378///
379VOID FchInitResetSpi (IN VOID *FchDataPtr);
380VOID FchInitResetLpc (IN VOID *FchDataPtr);
381VOID FchInitResetLpcProgram (IN VOID *FchDataPtr);
382///
383/// Dxe Phase
384///
385VOID FchInitEnvSpi (IN VOID *FchDataPtr);
386VOID FchInitMidSpi (IN VOID *FchDataPtr);
387VOID FchInitLateSpi (IN VOID *FchDataPtr);
388VOID FchInitEnvLpc (IN VOID *FchDataPtr);
389VOID FchInitMidLpc (IN VOID *FchDataPtr);
390VOID FchInitLateLpc (IN VOID *FchDataPtr);
391VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr);
392///
393/// Other Public Routines
394///
395VOID FchSpiUnlock (IN VOID *FchDataPtr);
396VOID FchSpiLock (IN VOID *FchDataPtr);
397
398/*--------------------------- Documentation Pages ---------------------------*/
399VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
400VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
401VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
402VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
403VOID TurnOffCG2 (OUT VOID);
404VOID BackUpCG2 (OUT VOID);
405VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
406VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
407VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
408VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
409VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
410VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
411VOID AcLossControl (IN UINT8 AcLossControlValue);
412VOID FchVgaInit (OUT VOID);
413VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
414VOID ValidateFchVariant (IN VOID *FchDataPtr);
415VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
416BOOLEAN IsGCPU (IN VOID *FchDataPtr);
417BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
418VOID SbSleepTrapControl (IN BOOLEAN SleepTrap);
419
420AGESA_STATUS
421FchSpiTransfer (
422 IN UINT8 PrefixCode,
423 IN UINT8 Opcode,
424 IN OUT UINT8 *DataPtr,
425 IN UINT8 *AddressPtr,
426 IN UINT8 Length,
427 IN BOOLEAN WriteFlag,
428 IN BOOLEAN AddressFlag,
429 IN BOOLEAN DataFlag,
430 IN BOOLEAN FinishedFlag
431 );
432
433BOOLEAN
434FchPlatformSpiQe (
435 IN VOID *FchDataPtr
436 );
437
438#endif