Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD AGESA Basic Level Public APIs |
| 6 | * |
| 7 | * Contains basic Level Initialization routines. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: Interface |
| 12 | * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ |
| 13 | * |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 41 | ****************************************************************************** |
| 42 | */ |
| 43 | |
| 44 | |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | #include "AGESA.h" |
| 50 | #include "amdlib.h" |
| 51 | #include "Ids.h" |
| 52 | #include "cpuCacheInit.h" |
| 53 | #include "cpuRegisters.h" |
| 54 | #include "cpuApicUtilities.h" |
| 55 | #include "cpuEarlyInit.h" |
| 56 | #include "AdvancedApi.h" |
| 57 | #include "cpuServices.h" |
| 58 | #include "CommonInits.h" |
| 59 | #include "GnbInterface.h" |
| 60 | #include "Filecode.h" |
| 61 | #include "heapManager.h" |
| 62 | #include "CreateStruct.h" |
| 63 | CODE_GROUP (G1_PEICC) |
| 64 | RDATA_GROUP (G1_PEICC) |
| 65 | |
| 66 | #define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE |
| 67 | /*---------------------------------------------------------------------------------------- |
| 68 | * D E F I N I T I O N S A N D M A C R O S |
| 69 | *---------------------------------------------------------------------------------------- |
| 70 | */ |
| 71 | |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * T Y P E D E F S A N D S T R U C T U R E S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 77 | CONST EXECUTION_CACHE_REGION InitExeCacheMap[] = |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 78 | { |
| 79 | {0x00000000, 0x00000000}, |
| 80 | {0x00000000, 0x00000000}, |
| 81 | {0x00000000, 0x00000000} |
| 82 | }; |
| 83 | |
| 84 | /*---------------------------------------------------------------------------------------- |
| 85 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 86 | *---------------------------------------------------------------------------------------- |
| 87 | */ |
| 88 | AGESA_STATUS |
| 89 | AmdEarlyPlatformConfigInit ( |
| 90 | IN OUT PLATFORM_CONFIGURATION *PlatformConfig, |
| 91 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 92 | ); |
| 93 | |
| 94 | AGESA_STATUS |
| 95 | AllocateExecutionCacheInitializer ( |
| 96 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 97 | IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr |
| 98 | ); |
| 99 | /*---------------------------------------------------------------------------------------- |
| 100 | * E X P O R T E D F U N C T I O N S |
| 101 | *---------------------------------------------------------------------------------------- |
| 102 | */ |
| 103 | extern BUILD_OPT_CFG UserOptions; |
| 104 | /*------------------------------------------------------------------------------------*/ |
| 105 | /** |
| 106 | * Initialize AmdInitEarly stage platform profile and user option input. |
| 107 | * |
| 108 | * @param[in,out] PlatformConfig Platform profile/build option config structure |
| 109 | * @param[in,out] StdHeader AMD standard header config param |
| 110 | * |
| 111 | * @retval AGESA_SUCCESS Always Succeeds. |
| 112 | * |
| 113 | */ |
| 114 | AGESA_STATUS |
| 115 | AmdEarlyPlatformConfigInit ( |
| 116 | IN OUT PLATFORM_CONFIGURATION *PlatformConfig, |
| 117 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 118 | ) |
| 119 | { |
| 120 | CommonPlatformConfigInit (PlatformConfig, StdHeader); |
| 121 | |
| 122 | return AGESA_SUCCESS; |
| 123 | } |
| 124 | /*------------------------------------------------------------------------------------*/ |
| 125 | /** |
| 126 | * Initializer routine that will be invoked by the wrapper to initialize the input |
| 127 | * structure for the AllocateExecutionCache. |
| 128 | * |
| 129 | * @param[in] StdHeader Opaque handle to standard config header |
| 130 | * @param[in] AmdExeAddrMapPtr Our Service interface struct |
| 131 | * |
| 132 | * @retval AGESA_SUCCESS Always Succeeds. |
| 133 | * |
| 134 | */ |
| 135 | AGESA_STATUS |
| 136 | AllocateExecutionCacheInitializer ( |
| 137 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 138 | IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr |
| 139 | ) |
| 140 | { |
| 141 | UINT8 i; |
| 142 | ASSERT (AmdExeAddrMapPtr != NULL); |
| 143 | |
| 144 | for (i = 0; i < MAX_CACHE_REGIONS; ++i) { |
| 145 | AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr; |
| 146 | AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize; |
| 147 | } |
| 148 | |
| 149 | return AGESA_SUCCESS; |
| 150 | } |
| 151 | |
| 152 | /*---------------------------------------------------------------------------------------*/ |
| 153 | /** |
| 154 | * |
| 155 | * Initializer routine that will be invoked by the wrapper to initialize the input |
| 156 | * structure for the AmdInitEarly. |
| 157 | * |
| 158 | * @param[in] StdHeader AMD standard header config param. |
| 159 | * @param[in,out] EarlyParams The service interface struct to initialize. |
| 160 | * |
| 161 | * @retval AGESA_SUCCESS Always succeeds. |
| 162 | */ |
| 163 | AGESA_STATUS |
| 164 | AmdInitEarlyInitializer ( |
| 165 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 166 | IN OUT AMD_EARLY_PARAMS *EarlyParams |
| 167 | ) |
| 168 | { |
| 169 | ASSERT (StdHeader != NULL); |
| 170 | ASSERT (EarlyParams != NULL); |
| 171 | |
| 172 | EarlyParams->StdHeader = *StdHeader; |
| 173 | |
| 174 | // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED. |
| 175 | // |
| 176 | |
| 177 | AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]); |
| 178 | |
| 179 | AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig); |
| 180 | |
| 181 | AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader); |
| 182 | |
| 183 | return AGESA_SUCCESS; |
| 184 | } |
| 185 | |
| 186 | |
| 187 | /*---------------------------------------------------------------------------------------*/ |
| 188 | /** |
| 189 | * Perform initialization services required at the Early Init POST time point. |
| 190 | * |
| 191 | * Execution Cache, HyperTransport, and AP Init advanced services are performed. |
| 192 | * |
| 193 | * @param[in] EarlyParams The interface struct for all early services |
| 194 | * |
| 195 | * @return The most severe AGESA_STATUS returned by any called service. |
| 196 | * |
| 197 | */ |
| 198 | AGESA_STATUS |
| 199 | AmdInitEarly ( |
| 200 | IN OUT AMD_EARLY_PARAMS *EarlyParams |
| 201 | ) |
| 202 | { |
| 203 | AGESA_STATUS CalledAgesaStatus; |
| 204 | AGESA_STATUS EarlyInitStatus; |
| 205 | WARM_RESET_REQUEST Request; |
| 206 | UINT8 PrevRequestBit; |
| 207 | UINT8 PrevStateBits; |
| 208 | |
| 209 | IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITEARLY, &EarlyParams->StdHeader); |
| 210 | |
| 211 | AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader); |
| 212 | |
| 213 | EarlyInitStatus = AGESA_SUCCESS; |
| 214 | |
| 215 | // Setup ROM execution cache |
| 216 | IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n"); |
| 217 | CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]); |
| 218 | IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n"); |
| 219 | if (CalledAgesaStatus > EarlyInitStatus) { |
| 220 | EarlyInitStatus = CalledAgesaStatus; |
| 221 | } |
| 222 | |
| 223 | IDS_HDT_CONSOLE_DEBUG_CODE ( |
| 224 | { |
| 225 | extern CHAR8 *BldOptDebugOutput[]; |
| 226 | |
| 227 | UINT8 i; |
| 228 | for (i = 0; BldOptDebugOutput[i] != NULL; i++) { |
| 229 | IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]); |
| 230 | } |
| 231 | } |
| 232 | ) |
| 233 | |
| 234 | // |
| 235 | // WARNING: AGESA's own IDT is at heap which would be moved from one place to another |
| 236 | // so we MUST restore IDT every time before moving heap. |
| 237 | // |
| 238 | IDS_EXCEPTION_TRAP (IDS_IDT_REPLACE_IDTR_FOR_BSC, NULL, &EarlyParams->StdHeader); |
| 239 | ASSERT (EarlyParams != NULL); |
| 240 | PrevRequestBit = FALSE; |
| 241 | PrevStateBits = WR_STATE_COLD; |
| 242 | IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: Start %x \n\n", PrevStateBits); |
| 243 | // If a previously requested warm reset cannot be triggered in the |
| 244 | // current stage, store the previous state of request and reset the |
| 245 | // request struct to the current post stage |
| 246 | GetWarmResetFlag (&EarlyParams->StdHeader, &Request); |
| 247 | if (Request.RequestBit == TRUE) { |
| 248 | if (Request.StateBits >= Request.PostStage) { |
| 249 | PrevRequestBit = Request.RequestBit; |
| 250 | PrevStateBits = Request.StateBits; |
| 251 | Request.RequestBit = FALSE; |
| 252 | Request.StateBits = Request.PostStage - 1; |
| 253 | SetWarmResetFlag (&EarlyParams->StdHeader, &Request); |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader); |
| 258 | |
| 259 | // Full Hypertransport Initialization |
| 260 | // IMPORTANT: All AP cores call Ht Init. HT Init handles full init for the BSC, and map init for APs. |
| 261 | IDS_PERF_TIMESTAMP (TP_BEGINAMDHTINITIALIZE, &EarlyParams->StdHeader); |
| 262 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: Start\n"); |
| 263 | CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig); |
| 264 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: End\n"); |
| 265 | IDS_PERF_TIMESTAMP (TP_ENDAMDHTINITIALIZE, &EarlyParams->StdHeader); |
| 266 | if (CalledAgesaStatus > EarlyInitStatus) { |
| 267 | EarlyInitStatus = CalledAgesaStatus; |
| 268 | } |
| 269 | |
| 270 | IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATEARLIER, &EarlyParams->StdHeader); |
| 271 | CalledAgesaStatus = GnbInitAtEarlier (EarlyParams); |
| 272 | IDS_PERF_TIMESTAMP (TP_ENDGNBINITATEARLIER, &EarlyParams->StdHeader); |
| 273 | if (CalledAgesaStatus > EarlyInitStatus) { |
| 274 | EarlyInitStatus = CalledAgesaStatus; |
| 275 | } |
| 276 | |
| 277 | // AP launch |
| 278 | IDS_PERF_TIMESTAMP (TP_BEGINAMDCPUEARLY, &EarlyParams->StdHeader); |
| 279 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: Start\n"); |
| 280 | CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig); |
| 281 | IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: End\n"); |
| 282 | IDS_PERF_TIMESTAMP (TP_ENDAMDCPUEARLY, &EarlyParams->StdHeader); |
| 283 | if (CalledAgesaStatus > EarlyInitStatus) { |
| 284 | EarlyInitStatus = CalledAgesaStatus; |
| 285 | } |
| 286 | |
| 287 | // Warm Reset, should be at the end of AmdInitEarly |
| 288 | GetWarmResetFlag (&EarlyParams->StdHeader, &Request); |
| 289 | // If a warm reset is requested in the current post stage, trigger the |
| 290 | // warm reset and ignore the previous request |
| 291 | if (Request.RequestBit == TRUE) { |
| 292 | if (Request.StateBits < Request.PostStage) { |
| 293 | AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader); |
| 294 | } |
| 295 | } else { |
| 296 | // Otherwise, if there's a previous request, restore it |
| 297 | // so that the subsequent post stage can trigger the warm reset |
| 298 | if (PrevRequestBit == TRUE) { |
| 299 | Request.RequestBit = PrevRequestBit; |
| 300 | Request.StateBits = PrevStateBits; |
| 301 | SetWarmResetFlag (&EarlyParams->StdHeader, &Request); |
| 302 | } |
| 303 | } |
| 304 | |
| 305 | IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATEARLY, &EarlyParams->StdHeader); |
| 306 | CalledAgesaStatus = GnbInitAtEarly (EarlyParams); |
| 307 | IDS_PERF_TIMESTAMP (TP_ENDGNBINITATEARLY, &EarlyParams->StdHeader); |
| 308 | if (CalledAgesaStatus > EarlyInitStatus) { |
| 309 | EarlyInitStatus = CalledAgesaStatus; |
| 310 | } |
| 311 | // Check for Cache As Ram Corruption |
| 312 | IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader); |
| 313 | |
| 314 | IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader); |
| 315 | AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader); |
| 316 | IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: End\n\n"); |
| 317 | |
| 318 | // Flush out all debug contents in case warm reset is triggered after this point |
| 319 | IDS_HDT_CONSOLE_FLUSH_BUFFER (&EarlyParams->StdHeader); |
| 320 | IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITEARLY, &EarlyParams->StdHeader); |
| 321 | |
| 322 | return EarlyInitStatus; |
| 323 | } |