Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * ACPI S3 support definitions. |
| 6 | * |
| 7 | * @xrefitem bom "File Content Label" "Release Content" |
| 8 | * @e project: AGESA |
| 9 | * @e sub-project: CPU |
| 10 | * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ |
| 11 | * |
| 12 | */ |
| 13 | /* |
| 14 | ***************************************************************************** |
| 15 | * |
| 16 | * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| 17 | * All rights reserved. |
| 18 | * |
| 19 | * Redistribution and use in source and binary forms, with or without |
| 20 | * modification, are permitted provided that the following conditions are met: |
| 21 | * * Redistributions of source code must retain the above copyright |
| 22 | * notice, this list of conditions and the following disclaimer. |
| 23 | * * Redistributions in binary form must reproduce the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer in the |
| 25 | * documentation and/or other materials provided with the distribution. |
| 26 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 27 | * its contributors may be used to endorse or promote products derived |
| 28 | * from this software without specific prior written permission. |
| 29 | * |
| 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 31 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 32 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 33 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 34 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 35 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 37 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 38 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 39 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 40 | * *************************************************************************** |
| 41 | * |
| 42 | */ |
| 43 | |
| 44 | #ifndef _S3_H_ |
| 45 | #define _S3_H_ |
| 46 | |
| 47 | |
| 48 | /*--------------------------------------------------------------------------------------- |
| 49 | * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) |
| 50 | *--------------------------------------------------------------------------------------- |
| 51 | */ |
| 52 | |
| 53 | |
| 54 | /*--------------------------------------------------------------------------------------- |
| 55 | * D E F I N I T I O N S A N D M A C R O S |
| 56 | *--------------------------------------------------------------------------------------- |
| 57 | */ |
| 58 | #define RESTART_FROM_BEGINNING_LIST 0xFFFFFFFFul |
| 59 | |
| 60 | /*--------------------------------------------------------------------------------------- |
| 61 | * T Y P E D E F S, S T R U C T U R E S, E N U M S |
| 62 | *--------------------------------------------------------------------------------------- |
| 63 | */ |
| 64 | |
| 65 | /* Device related definitions */ |
| 66 | |
| 67 | /// Header at the beginning of a context save buffer. |
| 68 | typedef struct { |
| 69 | UINT16 Version; ///< Version of header |
| 70 | UINT16 NumDevices; ///< Number of devices in the list |
| 71 | UINT16 RelativeOrMaskOffset; ///< Size of device list + header |
| 72 | UINT32 NextBlockOffset; ///< Size of the whole device save context |
| 73 | } DEVICE_BLOCK_HEADER; |
| 74 | |
| 75 | /// S3 device types |
| 76 | typedef enum { |
| 77 | DEV_TYPE_PCI_PRE_ESR, ///< PCI device before exiting self-refresh |
| 78 | DEV_TYPE_PCI, ///< PCI device after exiting self-refresh |
| 79 | DEV_TYPE_CPCI_PRE_ESR, ///< 'conditional' PCI device before exiting self-refresh |
| 80 | DEV_TYPE_CPCI, ///< 'conditional' PCI device after exiting self-refresh |
| 81 | DEV_TYPE_MSR_PRE_ESR, ///< MSR device before exiting self-refresh |
| 82 | DEV_TYPE_MSR, ///< MSR device after exiting self-refresh |
| 83 | DEV_TYPE_CMSR_PRE_ESR, ///< 'conditional' MSR device before exiting self-refresh |
| 84 | DEV_TYPE_CMSR ///< 'conditional' MSR device after exiting self-refresh |
| 85 | } S3_DEVICE_TYPES; |
| 86 | |
| 87 | /// S3 restoration call points |
| 88 | typedef enum { |
| 89 | INIT_RESUME, ///< AMD_INIT_RESUME |
| 90 | S3_LATE_RESTORE ///< AMD_S3LATE_RESTORE |
| 91 | } CALL_POINTS; |
| 92 | |
| 93 | /// S3 device common header |
| 94 | typedef struct { |
| 95 | UINT32 RegisterListID; ///< Unique ID of this device |
| 96 | UINT8 Type; ///< Appropriate S3_DEVICE_TYPES type |
| 97 | } DEVICE_DESCRIPTOR; |
| 98 | |
| 99 | /// S3 PCI device header |
| 100 | typedef struct { |
| 101 | UINT32 RegisterListID; ///< Unique ID of this device |
| 102 | UINT8 Type; ///< DEV_TYPE_PCI / DEV_TYPE_PCI_PRE_ESR |
| 103 | UINT8 Node; ///< Zero-based node number |
| 104 | } PCI_DEVICE_DESCRIPTOR; |
| 105 | |
| 106 | /// S3 'conditional' PCI device header |
| 107 | typedef struct { |
| 108 | UINT32 RegisterListID; ///< Unique ID of this device |
| 109 | UINT8 Type; ///< DEV_TYPE_CPCI / DEV_TYPE_CPCI_PRE_ESR |
| 110 | UINT8 Node; ///< Zero-based node number |
| 111 | UINT8 Mask1; ///< Conditional mask 1 |
| 112 | UINT8 Mask2; ///< Conditional mask 2 |
| 113 | } CONDITIONAL_PCI_DEVICE_DESCRIPTOR; |
| 114 | |
| 115 | /// S3 MSR device header |
| 116 | typedef struct { |
| 117 | UINT32 RegisterListID; ///< Unique ID of this device |
| 118 | UINT8 Type; ///< DEV_TYPE_MSR / DEV_TYPE_MSR_PRE_ESR |
| 119 | } MSR_DEVICE_DESCRIPTOR; |
| 120 | |
| 121 | /// S3 'conditional' MSR device header |
| 122 | typedef struct { |
| 123 | UINT32 RegisterListID; ///< Unique ID of this device |
| 124 | UINT8 Type; ///< DEV_TYPE_CMSR / DEV_TYPE_CMSR_PRE_ESR |
| 125 | UINT8 Mask1; ///< Conditional mask 1 |
| 126 | UINT8 Mask2; ///< Conditional mask 2 |
| 127 | } CONDITIONAL_MSR_DEVICE_DESCRIPTOR; |
| 128 | |
| 129 | /* Special case related definitions */ |
| 130 | |
| 131 | /** |
| 132 | * PCI special case save handler |
| 133 | * |
| 134 | * @param[in] AccessWidth 8, 16, or 32 bit wide access |
| 135 | * @param[in] Address full PCI address of the register to save |
| 136 | * @param[out] Value Value read from the register |
| 137 | * @param[in] ConfigPtr AMD standard header config parameter |
| 138 | * |
| 139 | */ |
| 140 | typedef VOID (*PF_S3_SPECIAL_PCI_SAVE) ( |
| 141 | IN ACCESS_WIDTH AccessWidth, |
| 142 | IN PCI_ADDR Address, |
| 143 | OUT VOID *Value, |
| 144 | IN VOID *ConfigPtr |
| 145 | ); |
| 146 | |
| 147 | /** |
| 148 | * PCI special case restore handler |
| 149 | * |
| 150 | * @param[in] AccessWidth 8, 16, or 32 bit wide access |
| 151 | * @param[in] Address full PCI address of the register to save |
| 152 | * @param[in] Value Value to write to the register |
| 153 | * @param[in] ConfigPtr AMD standard header config parameter |
| 154 | * |
| 155 | */ |
| 156 | typedef VOID (*PF_S3_SPECIAL_PCI_RESTORE) ( |
| 157 | IN ACCESS_WIDTH AccessWidth, |
| 158 | IN PCI_ADDR PciAddress, |
| 159 | IN VOID *Value, |
| 160 | IN VOID *StdHeader |
| 161 | ); |
| 162 | |
| 163 | /** |
| 164 | * MSR special case save handler |
| 165 | * |
| 166 | * @param[in] MsrAddress Address of model specific register to save |
| 167 | * @param[out] Value Value read from the register |
| 168 | * @param[in] ConfigPtr AMD standard header config parameter |
| 169 | * |
| 170 | */ |
| 171 | typedef VOID (*PF_S3_SPECIAL_MSR_SAVE) ( |
| 172 | IN UINT32 MsrAddress, |
| 173 | OUT UINT64 *Value, |
| 174 | IN VOID *StdHeader |
| 175 | ); |
| 176 | |
| 177 | /** |
| 178 | * MSR special case restore handler |
| 179 | * |
| 180 | * @param[in] MsrAddress Address of model specific register to restore |
| 181 | * @param[in] Value Value to write to the register |
| 182 | * @param[in] ConfigPtr AMD standard header config parameter |
| 183 | * |
| 184 | */ |
| 185 | typedef VOID (*PF_S3_SPECIAL_MSR_RESTORE) ( |
| 186 | IN UINT32 MsrAddress, |
| 187 | IN UINT64 *Value, |
| 188 | IN VOID *StdHeader |
| 189 | ); |
| 190 | |
| 191 | /// PCI special case save/restore structure. |
| 192 | typedef struct { |
| 193 | PF_S3_SPECIAL_PCI_SAVE Save; ///< Save routine |
| 194 | PF_S3_SPECIAL_PCI_RESTORE Restore; ///< Restore routine |
| 195 | } PCI_SPECIAL_CASE; |
| 196 | |
| 197 | /// MSR special case save/restore structure. |
| 198 | typedef struct { |
| 199 | PF_S3_SPECIAL_MSR_SAVE Save; ///< Save routine |
| 200 | PF_S3_SPECIAL_MSR_RESTORE Restore; ///< Restore routine |
| 201 | } MSR_SPECIAL_CASE; |
| 202 | |
| 203 | /* Register related definitions */ |
| 204 | /// S3 register type bit fields |
| 205 | typedef struct { |
| 206 | UINT8 SpecialCaseIndex:4; ///< Special Case array index |
| 207 | UINT8 RegisterSize:3; ///< For PCI, 1 = byte, 2 = word, else = dword. |
| 208 | ///< For MSR, don't care |
| 209 | UINT8 SpecialCaseFlag:1; ///< Indicates special case |
| 210 | } S3_REGISTER_TYPE; |
| 211 | |
| 212 | /// S3 PCI register descriptor. |
| 213 | typedef struct { |
| 214 | S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, |
| 215 | ///< Type[6:3] = register size in bytes, |
| 216 | ///< Type[2:0] = special case index |
| 217 | UINT8 Function; ///< PCI function of the register |
| 218 | UINT16 Offset; ///< PCI offset of the register |
| 219 | UINT32 AndMask; ///< AND mask to be applied to the value before saving |
| 220 | UINT8 BootMode; ///< Boot mode |
| 221 | } PCI_REG_DESCRIPTOR; |
| 222 | |
| 223 | /// S3 'conditional' PCI register descriptor. |
| 224 | typedef struct { |
| 225 | S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, |
| 226 | ///< Type[6:3] = register size in bytes, |
| 227 | ///< Type[2:0] = special case index |
| 228 | UINT8 Function; ///< PCI function of the register |
| 229 | UINT16 Offset; ///< PCI offset of the register |
| 230 | UINT32 AndMask; ///< AND mask to be applied to the value before saving |
| 231 | UINT8 Mask1; ///< conditional mask 1 |
| 232 | UINT8 Mask2; ///< conditional mask 2 |
| 233 | UINT8 BootMode; ///< Boot mode |
| 234 | } CONDITIONAL_PCI_REG_DESCRIPTOR; |
| 235 | |
| 236 | /// S3 MSR register descriptor. |
| 237 | typedef struct { |
| 238 | S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, |
| 239 | ///< Type[6:3] = reserved, |
| 240 | ///< Type[2:0] = special case index |
| 241 | UINT32 Address; ///< MSR address |
| 242 | UINT64 AndMask; ///< AND mask to be applied to the value before saving |
| 243 | UINT8 BootMode; ///< Boot mode |
| 244 | } MSR_REG_DESCRIPTOR; |
| 245 | |
| 246 | /// S3 'conditional' MSR register descriptor. |
| 247 | typedef struct { |
| 248 | S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, |
| 249 | ///< Type[6:3] = reserved, |
| 250 | ///< Type[2:0] = special case index |
| 251 | UINT32 Address; ///< MSR address |
| 252 | UINT64 AndMask; ///< AND mask to be applied to the value before saving |
| 253 | UINT8 Mask1; ///< conditional mask 1 |
| 254 | UINT8 Mask2; ///< conditional mask 2 |
| 255 | UINT8 BootMode; ///< Boot mode |
| 256 | } CONDITIONAL_MSR_REG_DESCRIPTOR; |
| 257 | |
| 258 | /// Common header at the beginning of an S3 register list. |
| 259 | typedef struct { |
| 260 | UINT16 Version; ///< Version of header |
| 261 | UINT16 NumRegisters; ///< Number of registers in the list |
| 262 | } REGISTER_BLOCK_HEADER; |
| 263 | |
| 264 | /// S3 PCI register list header. |
| 265 | typedef struct { |
| 266 | UINT16 Version; ///< Version of header |
| 267 | UINT16 NumRegisters; ///< Number of registers in the list |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 268 | CONST PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor |
| 269 | CONST PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 270 | } PCI_REGISTER_BLOCK_HEADER; |
| 271 | |
| 272 | /// S3 'conditional' PCI register list header. |
| 273 | typedef struct { |
| 274 | UINT16 Version; ///< Version of header |
| 275 | UINT16 NumRegisters; ///< Number of registers in the list |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 276 | CONST CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor |
| 277 | CONST PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 278 | } CPCI_REGISTER_BLOCK_HEADER; |
| 279 | |
| 280 | /// S3 MSR register list header. |
| 281 | typedef struct { |
| 282 | UINT16 Version; ///< Version of header |
| 283 | UINT16 NumRegisters; ///< Number of registers in the list |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 284 | CONST MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor |
| 285 | CONST MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 286 | } MSR_REGISTER_BLOCK_HEADER; |
| 287 | |
| 288 | /// S3 'conditional' MSR register list header. |
| 289 | typedef struct { |
| 290 | UINT16 Version; ///< Version of header |
| 291 | UINT16 NumRegisters; ///< Number of registers in the list |
| 292 | CONDITIONAL_MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor |
| 293 | MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers |
| 294 | } CMSR_REGISTER_BLOCK_HEADER; |
| 295 | |
| 296 | /// S3 device descriptor pointers for ease of proper pointer advancement. |
| 297 | typedef union { |
| 298 | DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header |
| 299 | PCI_DEVICE_DESCRIPTOR *PciDevice; ///< PCI header |
| 300 | CONDITIONAL_PCI_DEVICE_DESCRIPTOR *CPciDevice; ///< 'conditional' PCI header |
| 301 | MSR_DEVICE_DESCRIPTOR *MsrDevice; ///< MSR header |
| 302 | CONDITIONAL_MSR_DEVICE_DESCRIPTOR *CMsrDevice; ///< 'conditional' MSR header |
| 303 | } DEVICE_DESCRIPTORS; |
| 304 | |
| 305 | /// S3 register list header pointers for ease of proper pointer advancement. |
| 306 | typedef union { |
| 307 | DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header |
| 308 | PCI_REGISTER_BLOCK_HEADER *PciRegisters; ///< PCI header |
| 309 | CPCI_REGISTER_BLOCK_HEADER *CPciRegisters; ///< 'conditional' PCI header |
| 310 | MSR_REGISTER_BLOCK_HEADER *MsrRegisters; ///< MSR header |
| 311 | CMSR_REGISTER_BLOCK_HEADER *CMsrRegisters; ///< 'conditional' MSR header |
| 312 | } REGISTER_BLOCK_HEADERS; |
| 313 | |
| 314 | /// S3 Volatile Storage Header |
| 315 | typedef struct { |
| 316 | UINT32 HeapOffset; ///< Offset to beginning of heap data |
| 317 | UINT32 HeapSize; ///< Size of the heap data |
| 318 | UINT32 RegisterDataOffset; ///< Offset to beginning of raw save data |
| 319 | UINT32 RegisterDataSize; ///< Size of raw save data |
| 320 | } S3_VOLATILE_STORAGE_HEADER; |
| 321 | |
| 322 | |
| 323 | /*--------------------------------------------------------------------------------------- |
| 324 | * F U N C T I O N P R O T O T Y P E |
| 325 | *--------------------------------------------------------------------------------------- |
| 326 | */ |
| 327 | UINT32 |
| 328 | GetWorstCaseContextSize ( |
| 329 | IN DEVICE_BLOCK_HEADER *DeviceList, |
| 330 | IN CALL_POINTS CallPoint, |
| 331 | IN AMD_CONFIG_PARAMS *StdHeader |
| 332 | ); |
| 333 | |
| 334 | VOID |
| 335 | SaveDeviceListContext ( |
| 336 | IN DEVICE_BLOCK_HEADER *DeviceList, |
| 337 | IN VOID *Storage, |
| 338 | IN CALL_POINTS CallPoint, |
| 339 | OUT UINT32 *ActualBufferSize, |
| 340 | IN AMD_CONFIG_PARAMS *StdHeader |
| 341 | ); |
| 342 | |
| 343 | VOID |
| 344 | RestorePreESRContext ( |
| 345 | OUT VOID **OrMaskPtr, |
| 346 | IN VOID *Storage, |
| 347 | IN CALL_POINTS CallPoint, |
| 348 | IN AMD_CONFIG_PARAMS *StdHeader |
| 349 | ); |
| 350 | |
| 351 | VOID |
| 352 | RestorePostESRContext ( |
| 353 | IN VOID *OrMaskPtr, |
| 354 | IN VOID *Storage, |
| 355 | IN CALL_POINTS CallPoint, |
| 356 | IN AMD_CONFIG_PARAMS *StdHeader |
| 357 | ); |
| 358 | |
| 359 | VOID |
| 360 | AmdS3ParamsInitializer ( |
| 361 | OUT AMD_S3_PARAMS *S3Params |
| 362 | ); |
| 363 | |
| 364 | VOID |
| 365 | GetNonMemoryRelatedDeviceList ( |
| 366 | OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList, |
| 367 | IN AMD_CONFIG_PARAMS *StdHeader |
| 368 | ); |
| 369 | |
| 370 | AGESA_STATUS |
| 371 | S3GetPciDeviceRegisterList ( |
| 372 | IN PCI_DEVICE_DESCRIPTOR *Device, |
| 373 | OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, |
| 374 | IN AMD_CONFIG_PARAMS *StdHeader |
| 375 | ); |
| 376 | |
| 377 | AGESA_STATUS |
| 378 | S3GetCPciDeviceRegisterList ( |
| 379 | IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, |
| 380 | OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, |
| 381 | IN AMD_CONFIG_PARAMS *StdHeader |
| 382 | ); |
| 383 | |
| 384 | AGESA_STATUS |
| 385 | S3GetMsrDeviceRegisterList ( |
| 386 | IN MSR_DEVICE_DESCRIPTOR *Device, |
| 387 | OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, |
| 388 | IN AMD_CONFIG_PARAMS *StdHeader |
| 389 | ); |
| 390 | |
| 391 | AGESA_STATUS |
| 392 | S3GetCMsrDeviceRegisterList ( |
| 393 | IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, |
| 394 | OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, |
| 395 | IN AMD_CONFIG_PARAMS *StdHeader |
| 396 | ); |
| 397 | |
| 398 | |
| 399 | #endif // _S3_H_ |