Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Install of build option: GNB |
| 6 | * |
| 7 | * Contains AMD AGESA install macros and test conditions. Output is the |
| 8 | * defaults tables reflecting the User's build options selection. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: Options |
| 13 | * @e \$Revision: 87849 $ @e \$Date: 2013-02-11 15:37:58 -0600 (Mon, 11 Feb 2013) $ |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 41 | * |
| 42 | ***************************************************************************/ |
| 43 | |
| 44 | #ifndef _OPTION_GNB_INSTALL_H_ |
| 45 | #define _OPTION_GNB_INSTALL_H_ |
| 46 | |
| 47 | #include "S3SaveState.h" |
| 48 | /* This option is designed to be included into the platform solution install |
| 49 | * file. The platform solution install file will define the options status. |
| 50 | * Check to validate the definition |
| 51 | */ |
| 52 | |
| 53 | //--------------------------------------------------------------------------------------------------- |
| 54 | // Family installation |
| 55 | //--------------------------------------------------------------------------------------------------- |
| 56 | |
| 57 | |
| 58 | |
| 59 | #define GNB_TYPE_TN FALSE |
| 60 | #define GNB_TYPE_BK FALSE |
| 61 | #define GNB_TYPE_KV FALSE |
| 62 | #define GNB_TYPE_KB FALSE |
| 63 | #define GNB_TYPE_BK FALSE |
| 64 | #define GNB_TYPE_ML FALSE |
| 65 | |
| 66 | #if (OPTION_FAMILY15H_TN == TRUE) |
| 67 | #undef GNB_TYPE_TN |
| 68 | #define GNB_TYPE_TN TRUE |
| 69 | #endif |
| 70 | |
| 71 | |
| 72 | #if (OPTION_FAMILY16H_KB == TRUE) |
| 73 | #undef GNB_TYPE_KB |
| 74 | #define GNB_TYPE_KB TRUE |
| 75 | #endif |
| 76 | |
| 77 | |
| 78 | #if (GNB_TYPE_KB == TRUE || GNB_TYPE_TN == TRUE) |
| 79 | //--------------------------------------------------------------------------------------------------- |
| 80 | // Service installation |
| 81 | //--------------------------------------------------------------------------------------------------- |
| 82 | |
| 83 | #include "Gnb.h" |
| 84 | #include "GnbPcie.h" |
| 85 | #include "GnbGfx.h" |
| 86 | |
| 87 | #define SERVICES_POINTER NULL |
| 88 | #if (GNB_TYPE_TN == TRUE) |
| 89 | #include "GnbInitTNInstall.h" |
| 90 | #endif |
| 91 | #if (GNB_TYPE_KB == TRUE) |
| 92 | #include "GnbInitKBInstall.h" |
| 93 | #endif |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 94 | CONST GNB_SERVICE * CONST ServiceTable = SERVICES_POINTER; |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 95 | |
| 96 | //--------------------------------------------------------------------------------------------------- |
| 97 | // BUILD options |
| 98 | //--------------------------------------------------------------------------------------------------- |
| 99 | |
| 100 | #ifndef CFG_IGFX_AS_PCIE_EP |
| 101 | #define CFG_IGFX_AS_PCIE_EP TRUE |
| 102 | #endif |
| 103 | |
| 104 | #ifndef CFG_LCLK_DEEP_SLEEP_EN |
| 105 | #if (GNB_TYPE_TN == TRUE) |
| 106 | #define CFG_LCLK_DEEP_SLEEP_EN FALSE |
| 107 | #else |
| 108 | #define CFG_LCLK_DEEP_SLEEP_EN TRUE |
| 109 | #endif |
| 110 | #endif |
| 111 | |
| 112 | #ifndef CFG_LCLK_DPM_EN |
| 113 | #define CFG_LCLK_DPM_EN TRUE |
| 114 | #endif |
| 115 | |
| 116 | #ifndef CFG_GMC_POWER_GATING |
| 117 | #if ((GNB_TYPE_TN == TRUE) || (GNB_TYPE_KB == TRUE)) |
| 118 | #define CFG_GMC_POWER_GATING GmcPowerGatingWithStutter |
| 119 | #else |
| 120 | #define CFG_GMC_POWER_GATING GmcPowerGatingDisabled |
| 121 | #endif |
| 122 | #endif |
| 123 | |
| 124 | #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE |
| 125 | #if (GNB_TYPE_TN == TRUE) |
| 126 | #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE |
| 127 | #else |
| 128 | #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE |
| 129 | #endif |
| 130 | #endif |
| 131 | |
| 132 | #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE |
| 133 | #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE |
| 134 | #endif |
| 135 | |
| 136 | #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT |
| 137 | #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE |
| 138 | #endif |
| 139 | |
| 140 | #ifndef CFG_GNB_LOAD_REAL_FUSE |
| 141 | #define CFG_GNB_LOAD_REAL_FUSE TRUE |
| 142 | #endif |
| 143 | |
| 144 | #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING |
| 145 | #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) |
| 146 | #endif |
| 147 | |
| 148 | #ifndef CFG_GNB_PCIE_LINK_L0_POOLING |
| 149 | #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) |
| 150 | #endif |
| 151 | |
| 152 | #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME |
| 153 | #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) |
| 154 | #endif |
| 155 | |
| 156 | #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME |
| 157 | #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) |
| 158 | #endif |
| 159 | |
| 160 | #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM |
| 161 | #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM |
| 162 | #else |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 163 | #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 164 | #endif |
| 165 | |
| 166 | #ifndef CFG_GNB_FORCE_CABLESAFE_OFF |
| 167 | #define CFG_GNB_FORCE_CABLESAFE_OFF FALSE |
| 168 | #endif |
| 169 | |
| 170 | #ifndef CFG_ORB_CLOCK_GATING_ENABLE |
| 171 | #define CFG_ORB_CLOCK_GATING_ENABLE TRUE |
| 172 | #endif |
| 173 | |
| 174 | #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS |
| 175 | #define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0 |
| 176 | #endif |
| 177 | |
| 178 | |
| 179 | #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE |
| 180 | #if (GNB_TYPE_TN == TRUE) |
| 181 | #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE TRUE |
| 182 | #else |
| 183 | #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE |
| 184 | #endif |
| 185 | #endif |
| 186 | |
| 187 | #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE |
| 188 | #if (GNB_TYPE_TN == TRUE) |
| 189 | #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE TRUE |
| 190 | #else |
| 191 | #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE |
| 192 | #endif |
| 193 | #endif |
| 194 | |
| 195 | #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE |
| 196 | #if (GNB_TYPE_TN == TRUE) |
| 197 | #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE TRUE |
| 198 | #else |
| 199 | #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE |
| 200 | #endif |
| 201 | #endif |
| 202 | |
| 203 | #ifndef CFG_GNB_ALTVDDNB_SUPPORT |
| 204 | #define CFG_GNB_ALTVDDNB_SUPPORT TRUE |
| 205 | #endif |
| 206 | |
| 207 | #ifndef CFG_GNB_BAPM_SUPPORT |
| 208 | #if ((GNB_TYPE_TN == TRUE) || (GNB_TYPE_KB == TRUE)) |
| 209 | #define CFG_GNB_BAPM_SUPPORT TRUE |
| 210 | #else |
| 211 | #define CFG_GNB_BAPM_SUPPORT FALSE |
| 212 | #endif |
| 213 | #endif |
| 214 | |
| 215 | #ifndef CFG_GNB_LHTC_SUPPORT |
| 216 | #if (GNB_TYPE_KB == TRUE) |
| 217 | #define CFG_GNB_LHTC_SUPPORT TRUE |
| 218 | #else |
| 219 | #define CFG_GNB_LHTC_SUPPORT FALSE |
| 220 | #endif |
| 221 | #endif |
| 222 | |
| 223 | #ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE |
| 224 | #define CFG_UNUSED_SIMD_POWERGATING_ENABLE TRUE |
| 225 | #endif |
| 226 | |
| 227 | #ifndef CFG_UNUSED_RB_POWERGATING_ENABLE |
| 228 | #define CFG_UNUSED_RB_POWERGATING_ENABLE FALSE |
| 229 | #endif |
| 230 | |
| 231 | #ifndef CFG_NBDPM_ENABLE |
| 232 | #if ((GNB_TYPE_KB == TRUE)) |
| 233 | #define CFG_NBDPM_ENABLE FALSE |
| 234 | #else |
| 235 | #define CFG_NBDPM_ENABLE TRUE |
| 236 | #endif |
| 237 | #endif |
| 238 | |
| 239 | #ifndef CFG_MAX_PAYLOAD_ENABLE |
| 240 | #define CFG_MAX_PAYLOAD_ENABLE TRUE |
| 241 | #endif |
| 242 | |
| 243 | |
| 244 | #ifndef CFG_ORB_DYN_WAKE_ENABLE |
| 245 | #if (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 246 | #define CFG_ORB_DYN_WAKE_ENABLE TRUE |
| 247 | #else |
| 248 | #define CFG_ORB_DYN_WAKE_ENABLE TRUE |
| 249 | #endif |
| 250 | #endif |
| 251 | |
| 252 | #ifndef CFG_LOADLINE_ENABLE |
| 253 | #define CFG_LOADLINE_ENABLE TRUE |
| 254 | #endif |
| 255 | |
| 256 | #ifndef CFG_PCIE_PHY_ISOLATION_SUPPORT |
| 257 | #if (GNB_TYPE_KB == TRUE) |
| 258 | #define CFG_PCIE_PHY_ISOLATION_SUPPORT TRUE |
| 259 | #else |
| 260 | #define CFG_PCIE_PHY_ISOLATION_SUPPORT FALSE |
| 261 | #endif |
| 262 | #endif |
| 263 | |
| 264 | #ifndef CFG_SVI_REVISION |
| 265 | #if (GNB_TYPE_KB == TRUE || GNB_TYPE_TN == TRUE) |
| 266 | #define CFG_SVI_REVISION 2 |
| 267 | #else |
| 268 | #define CFG_SVI_REVISION 1 |
| 269 | #endif |
| 270 | #endif |
| 271 | |
| 272 | #ifndef CFG_SCS_SUPPORT |
| 273 | #if ((GNB_TYPE_KB == TRUE)) |
| 274 | #define CFG_SCS_SUPPORT TRUE |
| 275 | #else |
| 276 | #define CFG_SCS_SUPPORT FALSE |
| 277 | #endif |
| 278 | #endif |
| 279 | |
| 280 | #ifndef CFG_SAMU_PATCH_ENABLED |
| 281 | #define CFG_SAMU_PATCH_ENABLED TRUE |
| 282 | #endif |
| 283 | |
| 284 | #ifndef CFG_GNB_TDC_SUPPORT |
| 285 | #define CFG_GNB_TDC_SUPPORT TRUE |
| 286 | #endif |
| 287 | #ifndef CFG_NATIVE_GEN1_PLL_ENABLE |
| 288 | #define CFG_NATIVE_GEN1_PLL_ENABLE TRUE |
| 289 | #endif |
| 290 | |
| 291 | #ifndef CFG_UMA_STEERING |
| 292 | #define CFG_UMA_STEERING 0 |
| 293 | #endif |
| 294 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 295 | CONST GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 296 | CFG_IGFX_AS_PCIE_EP, |
| 297 | CFG_LCLK_DEEP_SLEEP_EN, |
| 298 | CFG_LCLK_DPM_EN, |
| 299 | CFG_GMC_POWER_GATING, |
| 300 | CFG_SMU_SCLK_CLOCK_GATING_ENABLE, |
| 301 | CFG_PCIE_ASPM_BLACK_LIST_ENABLE, |
| 302 | CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT, |
| 303 | CFG_GNB_LOAD_REAL_FUSE, |
| 304 | CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, |
| 305 | CFG_GNB_PCIE_LINK_L0_POOLING, |
| 306 | CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, |
| 307 | CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, |
| 308 | CFG_GNB_PCIE_TRAINING_ALGORITHM, |
| 309 | CFG_GNB_FORCE_CABLESAFE_OFF, |
| 310 | CFG_ORB_CLOCK_GATING_ENABLE, |
| 311 | CFG_GNB_PCIE_POWERGATING_FLAGS, |
| 312 | TRUE, |
| 313 | CFG_IOC_SCLK_CLOCK_GATING_ENABLE, |
| 314 | CFG_IOMMU_L1_CLOCK_GATING_ENABLE, |
| 315 | CFG_IOMMU_L2_CLOCK_GATING_ENABLE, |
| 316 | CFG_GNB_ALTVDDNB_SUPPORT, |
| 317 | CFG_GNB_BAPM_SUPPORT, |
| 318 | CFG_UNUSED_SIMD_POWERGATING_ENABLE, |
| 319 | CFG_UNUSED_RB_POWERGATING_ENABLE, |
| 320 | CFG_NBDPM_ENABLE, |
| 321 | TRUE, |
| 322 | CFG_MAX_PAYLOAD_ENABLE, |
| 323 | CFG_ORB_DYN_WAKE_ENABLE, |
| 324 | CFG_LOADLINE_ENABLE, |
| 325 | CFG_PCIE_PHY_ISOLATION_SUPPORT, |
| 326 | CFG_GNB_LHTC_SUPPORT, |
| 327 | CFG_SVI_REVISION, |
| 328 | CFG_SCS_SUPPORT, |
| 329 | CFG_SAMU_PATCH_ENABLED, |
| 330 | {CFG_ACPI_SET_OEM_ID}, |
| 331 | {CFG_ACPI_SET_OEM_TABLE_ID}, |
| 332 | CFG_GNB_TDC_SUPPORT, |
| 333 | TRUE, |
| 334 | CFG_NATIVE_GEN1_PLL_ENABLE, |
| 335 | CFG_UMA_STEERING |
| 336 | }; |
| 337 | |
| 338 | //--------------------------------------------------------------------------------------------------- |
| 339 | // SMU Firmware |
| 340 | //--------------------------------------------------------------------------------------------------- |
| 341 | |
| 342 | |
| 343 | |
| 344 | //--------------------------------------------------------------------------------------------------- |
| 345 | // Module entries |
| 346 | //--------------------------------------------------------------------------------------------------- |
| 347 | |
| 348 | #if (AGESA_ENTRY_INIT_EARLY == TRUE) |
| 349 | //--------------------------------------------------------------------------------------------------- |
| 350 | #ifndef OPTION_NB_EARLY_INIT |
| 351 | #define OPTION_NB_EARLY_INIT TRUE |
| 352 | #endif |
| 353 | #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 354 | OPTION_GNB_FEATURE GnbEarlyInterfaceTN; |
| 355 | #define OPTION_GNBEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlyInterfaceTN, TpGnbEarlyInterface}, |
| 356 | #else |
| 357 | #define OPTION_GNBEARLYINTERFACETN_ENTRY |
| 358 | #endif |
| 359 | #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 360 | OPTION_GNB_FEATURE GnbEarlyInterfaceKB; |
| 361 | #define OPTION_GNBEARLYINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbEarlyInterfaceKB, TpGnbEarlyInterface}, |
| 362 | #else |
| 363 | #define OPTION_GNBEARLYINTERFACEKB_ENTRY |
| 364 | #endif |
| 365 | //--------------------------------------------------------------------------------------------------- |
| 366 | #ifndef OPTION_PCIE_CONFIG_MAP |
| 367 | #define OPTION_PCIE_CONFIG_MAP TRUE |
| 368 | #endif |
| 369 | #if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 370 | OPTION_GNB_FEATURE PcieConfigurationMap; |
| 371 | #define OPTION_PCIECONFIGURATIONMAP_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieConfigurationMap, TpGnbPcieConfigurationMap}, |
| 372 | #else |
| 373 | #define OPTION_PCIECONFIGURATIONMAP_ENTRY |
| 374 | #endif |
| 375 | //--------------------------------------------------------------------------------------------------- |
| 376 | #ifndef OPTION_PCIE_EARLY_INIT |
| 377 | #define OPTION_PCIE_EARLY_INIT TRUE |
| 378 | #endif |
| 379 | #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 380 | OPTION_GNB_FEATURE PcieEarlyInterfaceTN; |
| 381 | #define OPTION_PCIEEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEarlyInterfaceTN, TpGnbPcieEarlyInterface}, |
| 382 | #else |
| 383 | #define OPTION_PCIEEARLYINTERFACETN_ENTRY |
| 384 | #endif |
| 385 | #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 386 | OPTION_GNB_FEATURE PcieEarlyInterfaceKB; |
| 387 | #define OPTION_PCIEEARLYINTERFACEKB_ENTRY {AMD_FAMILY_KB, PcieEarlyInterfaceKB, TpGnbPcieEarlyInterface}, |
| 388 | #else |
| 389 | #define OPTION_PCIEEARLYINTERFACEKB_ENTRY |
| 390 | #endif |
| 391 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 392 | CONST OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 393 | OPTION_GNBEARLYINTERFACETN_ENTRY |
| 394 | OPTION_GNBEARLYINTERFACEKB_ENTRY |
| 395 | OPTION_PCIECONFIGURATIONMAP_ENTRY |
| 396 | OPTION_PCIEEARLYINTERFACETN_ENTRY |
| 397 | OPTION_PCIEEARLYINTERFACEKB_ENTRY |
| 398 | {0, NULL, EndGnbTestPoints} |
| 399 | }; |
| 400 | |
| 401 | //--------------------------------------------------------------------------------------------------- |
| 402 | #ifndef OPTION_PCIE_CONFIG_INIT |
| 403 | #define OPTION_PCIE_CONFIG_INIT TRUE |
| 404 | #endif |
| 405 | #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 406 | OPTION_GNB_FEATURE PcieConfigurationInit; |
| 407 | #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieConfigurationInit, TpGnbEarlierPcieConfigurationInit}, |
| 408 | #else |
| 409 | #define OPTION_PCIECONFIGURATIONINIT_ENTRY |
| 410 | #endif |
| 411 | //--------------------------------------------------------------------------------------------------- |
| 412 | #ifndef OPTION_NB_EARLIER_INIT |
| 413 | #define OPTION_NB_EARLIER_INIT TRUE |
| 414 | #endif |
| 415 | #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 416 | OPTION_GNB_FEATURE GnbEarlierInterfaceTN; |
| 417 | #define OPTION_GNBEARLIERINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlierInterfaceTN, TpGnbEarlierInterface}, |
| 418 | #else |
| 419 | #define OPTION_GNBEARLIERINTERFACETN_ENTRY |
| 420 | #endif |
| 421 | #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 422 | OPTION_GNB_FEATURE GnbEarlierInterfaceKB; |
| 423 | #define OPTION_GNBEARLIERINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbEarlierInterfaceKB, TpGnbEarlierInterface}, |
| 424 | #else |
| 425 | #define OPTION_GNBEARLIERINTERFACEKB_ENTRY |
| 426 | #endif |
| 427 | |
| 428 | #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 429 | OPTION_GNB_FEATURE OptionGnbInstall581; |
| 430 | #define OPTION_GNBSCSINTERFACEKB_ENTRY {AMD_FAMILY_KB, OptionGnbInstall581, TpGnbEarlierInterface}, |
| 431 | #else |
| 432 | #define OPTION_GNBSCSINTERFACEKB_ENTRY |
| 433 | #endif |
| 434 | |
| 435 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 436 | CONST OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 437 | OPTION_PCIECONFIGURATIONINIT_ENTRY |
| 438 | OPTION_GNBEARLIERINTERFACETN_ENTRY |
| 439 | OPTION_GNBEARLIERINTERFACEKB_ENTRY |
| 440 | OPTION_GNBSCSINTERFACEKB_ENTRY |
| 441 | {0, NULL, EndGnbTestPoints} |
| 442 | }; |
| 443 | #endif |
| 444 | |
| 445 | #if (AGESA_ENTRY_INIT_POST == TRUE) |
| 446 | //--------------------------------------------------------------------------------------------------- |
| 447 | #ifndef OPTION_GFX_CONFIG_POST_INIT |
| 448 | #define OPTION_GFX_CONFIG_POST_INIT TRUE |
| 449 | #endif |
| 450 | #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 451 | OPTION_GNB_FEATURE GfxConfigPostInterface; |
| 452 | #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigPostInterface, TpGnbGfxConfigPostInterface}, |
| 453 | #else |
| 454 | #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY |
| 455 | #endif |
| 456 | //--------------------------------------------------------------------------------------------------- |
| 457 | #ifndef OPTION_GFX_POST_INIT |
| 458 | #define OPTION_GFX_POST_INIT TRUE |
| 459 | #endif |
| 460 | #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 461 | OPTION_GNB_FEATURE GfxPostInterfaceTN; |
| 462 | #define OPTION_GFXPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxPostInterfaceTN, TpGnbGfxPostInterface}, |
| 463 | #else |
| 464 | #define OPTION_GFXPOSTINTERFACETN_ENTRY |
| 465 | #endif |
| 466 | #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 467 | OPTION_GNB_FEATURE GfxPostInterfaceKB; |
| 468 | #define OPTION_GFXPOSTINTERFACEKB_ENTRY {AMD_FAMILY_KB, GfxPostInterfaceKB, TpGnbGfxPostInterface}, |
| 469 | #else |
| 470 | #define OPTION_GFXPOSTINTERFACEKB_ENTRY |
| 471 | #endif |
| 472 | |
| 473 | //--------------------------------------------------------------------------------------------------- |
| 474 | #ifndef OPTION_NB_POST_INIT |
| 475 | #define OPTION_NB_POST_INIT TRUE |
| 476 | #endif |
| 477 | #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 478 | OPTION_GNB_FEATURE GnbPostInterfaceTN; |
| 479 | #define OPTION_GNBPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbPostInterfaceTN, TpGnbPostInterface}, |
| 480 | #else |
| 481 | #define OPTION_GNBPOSTINTERFACETN_ENTRY |
| 482 | #endif |
| 483 | #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 484 | OPTION_GNB_FEATURE GnbPostInterfaceKB; |
| 485 | #define OPTION_GNBPOSTINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbPostInterfaceKB, TpGnbPostInterface}, |
| 486 | #else |
| 487 | #define OPTION_GNBPOSTINTERFACEKB_ENTRY |
| 488 | #endif |
| 489 | |
| 490 | //--------------------------------------------------------------------------------------------------- |
| 491 | #ifndef OPTION_PCIE_POST_EARLY_INIT |
| 492 | #define OPTION_PCIE_POST_EARLY_INIT TRUE |
| 493 | #endif |
| 494 | #if (OPTION_PCIE_POST_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 495 | OPTION_GNB_FEATURE PciePostEarlyInterfaceTN; |
| 496 | #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostEarlyInterfaceTN, TpGnbPciePostEarlyInterface}, |
| 497 | #else |
| 498 | #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY |
| 499 | #endif |
| 500 | #if (OPTION_PCIE_POST_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 501 | OPTION_GNB_FEATURE PciePostEarlyInterfaceKB; |
| 502 | #define OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY {AMD_FAMILY_KB, PciePostEarlyInterfaceKB, TpGnbPciePostEarlyInterface}, |
| 503 | #else |
| 504 | #define OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY |
| 505 | #endif |
| 506 | |
| 507 | //--------------------------------------------------------------------------------------------------- |
| 508 | #ifndef OPTION_PCIE_POST_INIT |
| 509 | #define OPTION_PCIE_POST_INIT TRUE |
| 510 | #endif |
| 511 | #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 512 | OPTION_GNB_FEATURE PciePostInterfaceTN; |
| 513 | #define OPTION_PCIEPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostInterfaceTN, TpGnbPciePostInterface}, |
| 514 | #else |
| 515 | #define OPTION_PCIEPOSTINTERFACETN_ENTRY |
| 516 | #endif |
| 517 | #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 518 | OPTION_GNB_FEATURE PciePostInterfaceKB; |
| 519 | #define OPTION_PCIEPOSTINTERFACEKB_ENTRY {AMD_FAMILY_KB, PciePostInterfaceKB, TpGnbPciePostInterface}, |
| 520 | #else |
| 521 | #define OPTION_PCIEPOSTINTERFACEKB_ENTRY |
| 522 | #endif |
| 523 | |
| 524 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 525 | CONST OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 526 | OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY |
| 527 | OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY |
| 528 | OPTION_GFXCONFIGPOSTINTERFACE_ENTRY |
| 529 | OPTION_GFXPOSTINTERFACETN_ENTRY |
| 530 | OPTION_GFXPOSTINTERFACEKB_ENTRY |
| 531 | {0, NULL, EndGnbTestPoints} |
| 532 | }; |
| 533 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 534 | CONST OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 535 | OPTION_GNBPOSTINTERFACETN_ENTRY |
| 536 | OPTION_GNBPOSTINTERFACEKB_ENTRY |
| 537 | OPTION_PCIEPOSTINTERFACETN_ENTRY |
| 538 | OPTION_PCIEPOSTINTERFACEKB_ENTRY |
| 539 | {0, NULL, EndGnbTestPoints} |
| 540 | }; |
| 541 | #endif |
| 542 | |
| 543 | #if (AGESA_ENTRY_INIT_ENV == TRUE) |
| 544 | //--------------------------------------------------------------------------------------------------- |
| 545 | #ifndef OPTION_NB_ENV_INIT |
| 546 | #define OPTION_NB_ENV_INIT TRUE |
| 547 | #endif |
| 548 | #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 549 | OPTION_GNB_FEATURE GnbEnvInterfaceTN; |
| 550 | #define OPTION_GNBENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEnvInterfaceTN, TpGnbEnvInterface}, |
| 551 | #else |
| 552 | #define OPTION_GNBENVINTERFACETN_ENTRY |
| 553 | #endif |
| 554 | #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 555 | OPTION_GNB_FEATURE GnbEnvInterfaceKB; |
| 556 | #define OPTION_GNBENVINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbEnvInterfaceKB, TpGnbEnvInterface}, |
| 557 | #else |
| 558 | #define OPTION_GNBENVINTERFACEKB_ENTRY |
| 559 | #endif |
| 560 | |
| 561 | //--------------------------------------------------------------------------------------------------- |
| 562 | #ifndef OPTION_GFX_CONFIG_ENV_INIT |
| 563 | #define OPTION_GFX_CONFIG_ENV_INIT TRUE |
| 564 | #endif |
| 565 | #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 566 | OPTION_GNB_FEATURE GfxConfigEnvInterface; |
| 567 | #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigEnvInterface, TpGnbGfxConfigEnvInterface}, |
| 568 | #else |
| 569 | #define OPTION_GFXCONFIGENVINTERFACE_ENTRY |
| 570 | #endif |
| 571 | |
| 572 | //--------------------------------------------------------------------------------------------------- |
| 573 | #ifndef OPTION_GFX_ENV_INIT |
| 574 | #define OPTION_GFX_ENV_INIT TRUE |
| 575 | #endif |
| 576 | #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 577 | OPTION_GNB_FEATURE GfxEnvInterfaceTN; |
| 578 | #define OPTION_GFXENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxEnvInterfaceTN, TpGnbGfxEnvInterface}, |
| 579 | #else |
| 580 | #define OPTION_GFXENVINTERFACETN_ENTRY |
| 581 | #endif |
| 582 | #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 583 | OPTION_GNB_FEATURE GfxEnvInterfaceKB; |
| 584 | #define OPTION_GFXENVINTERFACEKB_ENTRY {AMD_FAMILY_KB, GfxEnvInterfaceKB, TpGnbGfxEnvInterface}, |
| 585 | #else |
| 586 | #define OPTION_GFXENVINTERFACEKB_ENTRY |
| 587 | #endif |
| 588 | |
| 589 | //--------------------------------------------------------------------------------------------------- |
| 590 | #ifndef OPTION_PCIE_ENV_INIT |
| 591 | #define OPTION_PCIE_ENV_INIT TRUE |
| 592 | #endif |
| 593 | #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 594 | OPTION_GNB_FEATURE PcieEnvInterfaceTN; |
| 595 | #define OPTION_PCIEENVINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEnvInterfaceTN, TpGnbPcieEnvInterface}, |
| 596 | #else |
| 597 | #define OPTION_PCIEENVINTERFACETN_ENTRY |
| 598 | #endif |
| 599 | #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 600 | OPTION_GNB_FEATURE PcieEnvInterfaceKB; |
| 601 | #define OPTION_PCIEENVINTERFACEKB_ENTRY {AMD_FAMILY_KB, PcieEnvInterfaceKB, TpGnbPcieEnvInterface}, |
| 602 | #else |
| 603 | #define OPTION_PCIEENVINTERFACEKB_ENTRY |
| 604 | #endif |
| 605 | |
| 606 | //--------------------------------------------------------------------------------------------------- |
| 607 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 608 | CONST OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 609 | OPTION_GNBENVINTERFACETN_ENTRY |
| 610 | OPTION_GNBENVINTERFACEKB_ENTRY |
| 611 | OPTION_PCIEENVINTERFACETN_ENTRY |
| 612 | OPTION_PCIEENVINTERFACEKB_ENTRY |
| 613 | OPTION_GFXCONFIGENVINTERFACE_ENTRY |
| 614 | OPTION_GFXENVINTERFACETN_ENTRY |
| 615 | OPTION_GFXENVINTERFACEKB_ENTRY |
| 616 | {0, NULL, EndGnbTestPoints} |
| 617 | }; |
| 618 | #endif |
| 619 | |
| 620 | #if (AGESA_ENTRY_INIT_MID == TRUE) |
| 621 | //--------------------------------------------------------------------------------------------------- |
| 622 | #ifndef OPTION_GFX_MID_INIT |
| 623 | #define OPTION_GFX_MID_INIT TRUE |
| 624 | #endif |
| 625 | #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 626 | OPTION_GNB_FEATURE GfxMidInterfaceTN; |
| 627 | #define OPTION_GFXMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxMidInterfaceTN, TpGnbGfxMidInterface}, |
| 628 | #else |
| 629 | #define OPTION_GFXMIDINTERFACETN_ENTRY |
| 630 | #endif |
| 631 | #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 632 | OPTION_GNB_FEATURE GfxMidInterfaceKB; |
| 633 | #define OPTION_GFXMIDINTERFACEKB_ENTRY {AMD_FAMILY_KB, GfxMidInterfaceKB, TpGnbGfxMidInterface}, |
| 634 | #else |
| 635 | #define OPTION_GFXMIDINTERFACEKB_ENTRY |
| 636 | #endif |
| 637 | |
| 638 | //--------------------------------------------------------------------------------------------------- |
| 639 | #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT |
| 640 | #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE |
| 641 | #endif |
| 642 | #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 643 | OPTION_GNB_FEATURE GfxIntInfoTableInterfaceTN; |
| 644 | #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxIntInfoTableInterfaceTN}, |
| 645 | #else |
| 646 | #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY |
| 647 | #endif |
| 648 | #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 649 | OPTION_GNB_FEATURE GfxIntInfoTableInterfaceKB; |
| 650 | #define OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY {AMD_FAMILY_KB, GfxIntInfoTableInterfaceKB}, |
| 651 | #else |
| 652 | #define OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY |
| 653 | #endif |
| 654 | |
| 655 | //--------------------------------------------------------------------------------------------------- |
| 656 | #ifndef OPTION_PCIe_MID_INIT |
| 657 | #define OPTION_PCIe_MID_INIT TRUE |
| 658 | #endif |
| 659 | #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 660 | OPTION_GNB_FEATURE PcieMidInterfaceTN; |
| 661 | #define OPTION_PCIEMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieMidInterfaceTN, TpPcieMidInterface}, |
| 662 | #else |
| 663 | #define OPTION_PCIEMIDINTERFACETN_ENTRY |
| 664 | #endif |
| 665 | #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 666 | OPTION_GNB_FEATURE PcieMidInterfaceKB; |
| 667 | #define OPTION_PCIEMIDINTERFACEKB_ENTRY {AMD_FAMILY_KB, PcieMidInterfaceKB, TpPcieMidInterface}, |
| 668 | #else |
| 669 | #define OPTION_PCIEMIDINTERFACEKB_ENTRY |
| 670 | #endif |
| 671 | |
| 672 | //--------------------------------------------------------------------------------------------------- |
| 673 | #ifndef OPTION_NB_MID_INIT |
| 674 | #define OPTION_NB_MID_INIT TRUE |
| 675 | #endif |
| 676 | #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 677 | OPTION_GNB_FEATURE GnbMidInterfaceTN; |
| 678 | #define OPTION_GNBMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbMidInterfaceTN, TpGnbMidInterface}, |
| 679 | #else |
| 680 | #define OPTION_GNBMIDINTERFACETN_ENTRY |
| 681 | #endif |
| 682 | //--------------------------------------------------------------------------------------------------- |
| 683 | #ifndef OPTION_GFX_CONFIG_POST_INIT |
| 684 | #define OPTION_GFX_CONFIG_POST_INIT TRUE |
| 685 | #endif |
| 686 | #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 687 | OPTION_GNB_FEATURE GfxConfigMidInterface; |
| 688 | #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigMidInterface, TpGnbGfxConfigMidInterface}, |
| 689 | #else |
| 690 | #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY |
| 691 | #endif |
| 692 | //--------------------------------------------------------------------------------------------------- |
| 693 | #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE) |
| 694 | OPTION_GNB_FEATURE GnbMidInterfaceKB; |
| 695 | #define OPTION_GNBMIDINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbMidInterfaceKB, TpGnbMidInterface}, |
| 696 | #else |
| 697 | #define OPTION_GNBMIDINTERFACEKB_ENTRY |
| 698 | #endif |
| 699 | |
| 700 | //--------------------------------------------------------------------------------------------------- |
| 701 | #ifndef OPTION_PCIE_MAXPAYLOAD_INTERFACE |
| 702 | #define OPTION_PCIE_MAXPAYLOAD_INTERFACE TRUE |
| 703 | #endif |
| 704 | #if (OPTION_PCIE_MAXPAYLOAD_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE) |
| 705 | OPTION_GNB_FEATURE PcieMaxPayloadInterface; |
| 706 | #define OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieMaxPayloadInterface, TpGnbPcieMaxPayloadInterface}, |
| 707 | #else |
| 708 | #define OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY |
| 709 | #endif |
| 710 | //--------------------------------------------------------------------------------------------------- |
| 711 | #ifndef OPTION_PCIE_CLK_PM_INTERFACE |
| 712 | #define OPTION_PCIE_CLK_PM_INTERFACE FALSE |
| 713 | #if (GNB_TYPE_TN == TRUE && (OPTION_FS1_SOCKET_SUPPORT == TRUE || OPTION_FP1_SOCKET_SUPPORT == TRUE)) |
| 714 | #undef OPTION_PCIE_CLK_PM_INTERFACE |
| 715 | #define OPTION_PCIE_CLK_PM_INTERFACE TRUE |
| 716 | #endif |
| 717 | #if (GNB_TYPE_KB == TRUE) |
| 718 | #undef OPTION_PCIE_CLK_PM_INTERFACE |
| 719 | #define OPTION_PCIE_CLK_PM_INTERFACE TRUE |
| 720 | #endif |
| 721 | #endif |
| 722 | |
| 723 | #if (OPTION_PCIE_CLK_PM_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE) |
| 724 | OPTION_GNB_FEATURE PcieClkPmInterface; |
| 725 | #define OPTION_PCIECLKPMINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieClkPmInterface, TpGnbPcieClkPmInterface}, |
| 726 | #else |
| 727 | #define OPTION_PCIECLKPMINTERFACE_ENTRY |
| 728 | #endif |
| 729 | //--------------------------------------------------------------------------------------------------- |
| 730 | #ifndef OPTION_PCIE_ASPM_INTERFACE |
| 731 | #define OPTION_PCIE_ASPM_INTERFACE TRUE |
| 732 | #endif |
| 733 | #if (OPTION_PCIE_ASPM_INTERFACE == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 734 | OPTION_GNB_FEATURE PcieAspmInterface; |
| 735 | #define OPTION_PCIEASPMINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieAspmInterface, TpGnbPcieAspmInterface}, |
| 736 | #else |
| 737 | #define OPTION_PCIEASPMINTERFACE_ENTRY |
| 738 | #endif |
| 739 | //--------------------------------------------------------------------------------------------------- |
| 740 | #ifndef OPTION_GNB_IOAPIC_INTERFACE |
| 741 | #define OPTION_GNB_IOAPIC_INTERFACE TRUE |
| 742 | #endif |
| 743 | #if (OPTION_GNB_IOAPIC_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE) |
| 744 | OPTION_GNB_FEATURE GnbNbIoapicInterface; |
| 745 | #define OPTION_GNBNBIOAPICINTERFACE_ENTRY {AMD_FAMILY_KB, GnbNbIoapicInterface, TpGnbNbIoapicInterface}, |
| 746 | #else |
| 747 | #define OPTION_GNBNBIOAPICINTERFACE_ENTRY |
| 748 | #endif |
| 749 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 750 | CONST OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 751 | OPTION_GFXCONFIGMIDINTERFACE_ENTRY |
| 752 | OPTION_GFXMIDINTERFACETN_ENTRY |
| 753 | OPTION_GFXMIDINTERFACEKB_ENTRY |
| 754 | OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY |
| 755 | OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY |
| 756 | OPTION_PCIEMIDINTERFACETN_ENTRY |
| 757 | OPTION_PCIEMIDINTERFACEKB_ENTRY |
| 758 | OPTION_GNBMIDINTERFACETN_ENTRY |
| 759 | OPTION_GNBMIDINTERFACEKB_ENTRY |
| 760 | OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY |
| 761 | OPTION_PCIECLKPMINTERFACE_ENTRY |
| 762 | OPTION_PCIEASPMINTERFACE_ENTRY |
| 763 | OPTION_GNBNBIOAPICINTERFACE_ENTRY |
| 764 | {0, NULL, EndGnbTestPoints} |
| 765 | }; |
| 766 | #endif |
| 767 | |
| 768 | #if (AGESA_ENTRY_INIT_LATE == TRUE) |
| 769 | //--------------------------------------------------------------------------------------------------- |
| 770 | #ifndef OPTION_ALIB |
| 771 | #define OPTION_ALIB FALSE |
| 772 | #endif |
| 773 | #if (OPTION_ALIB == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 774 | #define ALIB_CALL_TABLE |
| 775 | #define ALIB_CALL_TABLEV2 |
| 776 | #if (GNB_TYPE_TN == TRUE) |
| 777 | #if ((OPTION_FM2_SOCKET_SUPPORT == TRUE) || (OPTION_FM2r2_SOCKET_SUPPORT == TRUE)) |
| 778 | extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo; |
| 779 | extern F_ALIB_GET PcieAlibGetBaseTableTNFM2; |
| 780 | F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFM2; |
| 781 | #undef ALIB_CALL_TABLE |
| 782 | #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, |
| 783 | #else |
| 784 | extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo; |
| 785 | extern F_ALIB_GET PcieAlibGetBaseTableTNFS1; |
| 786 | F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFS1; |
| 787 | extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo; |
| 788 | extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo; |
| 789 | #undef ALIB_CALL_TABLE |
| 790 | #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \ |
| 791 | PcieAlibUpdateVoltageInfo, \ |
| 792 | PcieAlibUpdatePcieInfo, |
| 793 | |
| 794 | #endif |
| 795 | #endif |
| 796 | |
| 797 | |
| 798 | #if (GNB_TYPE_KB == TRUE) |
| 799 | extern F_ALIB_GET PcieAlibGetBaseTableKB; |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 800 | F_ALIB_GET * CONST AlibGetBaseTableV2 = PcieAlibGetBaseTableKB; |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 801 | extern F_ALIB_UPDATE PcieAlibUpdateVoltageData; |
| 802 | extern F_ALIB_UPDATE PcieAlibUpdatePcieData; |
| 803 | #undef ALIB_CALL_TABLEV2 |
| 804 | #define ALIB_CALL_TABLEV2 PcieAlibUpdateVoltageData, \ |
| 805 | PcieAlibUpdatePcieData, |
| 806 | #endif |
| 807 | |
| 808 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 809 | F_ALIB_UPDATE* CONST AlibDispatchTable [] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 810 | ALIB_CALL_TABLE |
| 811 | NULL |
| 812 | }; |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 813 | F_ALIB_UPDATE* CONST AlibDispatchTableV2 [] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 814 | ALIB_CALL_TABLEV2 |
| 815 | NULL |
| 816 | }; |
| 817 | #if (GNB_TYPE_TN == TRUE) |
| 818 | OPTION_GNB_FEATURE PcieAlibFeature; |
| 819 | #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_TN, PcieAlibFeature, TpGnbPcieAlibFeature}, |
| 820 | #endif |
| 821 | #if ((GNB_TYPE_KB == TRUE)) |
| 822 | OPTION_GNB_FEATURE PcieAlibV2Feature; |
| 823 | #define OPTION_PCIEALIBV2FEATURE_ENTRY {AMD_FAMILY_KB, PcieAlibV2Feature, TpGnbPcieAlibFeature}, |
| 824 | #endif |
| 825 | #else |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 826 | F_ALIB_GET * CONST AlibGetBaseTable = NULL; |
| 827 | F_ALIB_GET * CONST AlibGetBaseTableV2 = NULL; |
| 828 | F_ALIB_UPDATE* CONST AlibDispatchTable [] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 829 | NULL |
| 830 | }; |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 831 | F_ALIB_UPDATE* CONST AlibDispatchTableV2 [] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 832 | NULL |
| 833 | }; |
| 834 | #define OPTION_PCIEALIBFEATURE_ENTRY |
| 835 | #define OPTION_PCIEALIBV2FEATURE_ENTRY |
| 836 | #endif |
| 837 | //--------------------------------------------------------------------------------------------------- |
| 838 | #ifndef OPTION_IOMMU_ACPI_IVRS |
| 839 | #if (CFG_IOMMU_SUPPORT == TRUE) |
| 840 | #define OPTION_IOMMU_ACPI_IVRS TRUE |
| 841 | #else |
| 842 | #define OPTION_IOMMU_ACPI_IVRS FALSE |
| 843 | #endif |
| 844 | #endif |
| 845 | #if (OPTION_IOMMU_ACPI_IVRS == TRUE) && (GNB_TYPE_TN == TRUE) |
| 846 | OPTION_GNB_FEATURE GnbIommuIvrsTable; |
| 847 | #define OPTIONIOMMUACPIIVRSLATE_ENTRY {AMD_FAMILY_TN, GnbIommuIvrsTable}, |
| 848 | #else |
| 849 | #define OPTIONIOMMUACPIIVRSLATE_ENTRY |
| 850 | #endif |
| 851 | #if (CFG_IOMMU_SUPPORT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 852 | OPTION_GNB_FEATURE GnbIommuScratchMemoryRangeInterface; |
| 853 | #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY {AMD_FAMILY_TN, GnbIommuScratchMemoryRangeInterface, TpGnbIommuIvrsTable}, |
| 854 | #else |
| 855 | #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY |
| 856 | #endif |
| 857 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 858 | CONST OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 859 | #if (GNB_TYPE_TN == TRUE) |
| 860 | OPTION_PCIEALIBFEATURE_ENTRY |
| 861 | #endif |
| 862 | #if ((GNB_TYPE_KB == TRUE)) |
| 863 | OPTION_PCIEALIBV2FEATURE_ENTRY |
| 864 | #endif |
| 865 | OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY |
| 866 | OPTIONIOMMUACPIIVRSLATE_ENTRY |
| 867 | {0, NULL, EndGnbTestPoints} |
| 868 | }; |
| 869 | #endif |
| 870 | |
| 871 | #if (AGESA_ENTRY_INIT_S3SAVE == TRUE) |
| 872 | //--------------------------------------------------------------------------------------------------- |
| 873 | #ifndef OPTION_GFX_INIT_SVIEW |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 874 | #define OPTION_GFX_INIT_SVIEW FALSE |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 875 | #endif |
| 876 | #if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 877 | OPTION_GNB_FEATURE GfxInitSview; |
| 878 | #define OPTION_GFXINITSVIEW_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxInitSview}, |
| 879 | #else |
| 880 | #define OPTION_GFXINITSVIEW_ENTRY |
| 881 | #endif |
| 882 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 883 | CONST OPTION_GNB_CONFIGURATION GnbS3SaveFeatureTable[] = { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 884 | OPTION_GFXINITSVIEW_ENTRY |
| 885 | {0, NULL, EndGnbTestPoints} |
| 886 | }; |
| 887 | #endif |
| 888 | |
| 889 | #if (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) |
| 890 | #define GNBS3RESTOREV4 |
| 891 | #define GNBS3RESTOREV7 |
| 892 | #if (GNB_TYPE_TN == TRUE) |
| 893 | S3_DISPATCH_FUNCTION GnbSmuServiceRequestV4S3Script; |
| 894 | #undef GNBS3RESTOREV4 |
| 895 | #define GNBS3RESTOREV4 {GnbSmuServiceRequestV4S3Script_ID, GnbSmuServiceRequestV4S3Script}, |
| 896 | #endif |
| 897 | #if (GNB_TYPE_KB == TRUE) |
| 898 | S3_DISPATCH_FUNCTION GnbSmuServiceRequestV7S3Script; |
| 899 | #undef GNBS3RESTOREV7 |
| 900 | #define GNBS3RESTOREV7 {GnbSmuServiceRequestV7S3Script_ID, GnbSmuServiceRequestV7S3Script}, |
| 901 | #endif |
| 902 | S3_DISPATCH_FUNCTION GnbLibStallS3Script; |
| 903 | #define PCIELATERESTORETN |
| 904 | #define PCIELATERESTOREKB |
| 905 | #define GFXSCLKRESTORETN |
| 906 | #if (GNB_TYPE_TN == TRUE) |
| 907 | S3_DISPATCH_FUNCTION PcieLateRestoreInitTNS3Script; |
| 908 | S3_DISPATCH_FUNCTION GfxRequestSclkTNS3Script; |
| 909 | #undef PCIELATERESTORETN |
| 910 | #define PCIELATERESTORETN {PcieLateRestoreTNS3Script_ID, PcieLateRestoreInitTNS3Script}, |
| 911 | #undef GFXSCLKRESTORETN |
| 912 | #define GFXSCLKRESTORETN {GfxRequestSclkTNS3Script_ID, GfxRequestSclkTNS3Script }, |
| 913 | #endif |
| 914 | #if (GNB_TYPE_KB == TRUE) |
| 915 | S3_DISPATCH_FUNCTION PcieLateRestoreInitKBS3Script; |
| 916 | #undef PCIELATERESTOREKB |
| 917 | #define PCIELATERESTOREKB {PcieLateRestoreKBS3Script_ID, PcieLateRestoreInitKBS3Script}, |
| 918 | #endif |
| 919 | #define GNB_S3_DISPATCH_FUNCTION_TABLE \ |
| 920 | GNBS3RESTOREV4 \ |
| 921 | GNBS3RESTOREV7 \ |
| 922 | PCIELATERESTORETN \ |
| 923 | GFXSCLKRESTORETN \ |
| 924 | PCIELATERESTOREKB \ |
| 925 | {GnbLibStallS3Script_ID, GnbLibStallS3Script}, |
| 926 | |
| 927 | |
| 928 | |
| 929 | #endif |
| 930 | |
| 931 | #endif |
| 932 | #endif // _OPTION_GNB_INSTALL_H_ |