Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Install of family 16h support |
| 6 | * |
| 7 | * This file generates the defaults tables for family 16h processors. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: Core |
| 12 | * @e \$Revision: 87264 $ @e \$Date: 2013-01-31 09:26:23 -0600 (Thu, 31 Jan 2013) $ |
| 13 | */ |
| 14 | /***************************************************************************** |
| 15 | * |
| 16 | * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| 17 | * All rights reserved. |
| 18 | * |
| 19 | * Redistribution and use in source and binary forms, with or without |
| 20 | * modification, are permitted provided that the following conditions are met: |
| 21 | * * Redistributions of source code must retain the above copyright |
| 22 | * notice, this list of conditions and the following disclaimer. |
| 23 | * * Redistributions in binary form must reproduce the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer in the |
| 25 | * documentation and/or other materials provided with the distribution. |
| 26 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 27 | * its contributors may be used to endorse or promote products derived |
| 28 | * from this software without specific prior written permission. |
| 29 | * |
| 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 31 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 32 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 33 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 34 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 35 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 37 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 38 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 39 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 40 | * |
| 41 | ***************************************************************************/ |
| 42 | |
| 43 | #ifndef _OPTION_FAMILY_16H_INSTALL_H_ |
| 44 | #define _OPTION_FAMILY_16H_INSTALL_H_ |
| 45 | |
| 46 | #include "OptionFamily16hEarlySample.h" |
| 47 | #include "cpuFamilyTranslation.h" |
| 48 | |
| 49 | |
| 50 | /* |
| 51 | * Pull in family specific services based on entry point |
| 52 | */ |
| 53 | |
| 54 | /* |
| 55 | * Common Family 16h routines |
| 56 | */ |
| 57 | |
| 58 | /* |
| 59 | * Install family 16h model 00h - 0Fh support |
| 60 | */ |
| 61 | #ifdef OPTION_FAMILY16H_KB |
| 62 | #if OPTION_FAMILY16H_KB == TRUE |
| 63 | extern CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableBeforeApLaunch; |
| 64 | extern CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableAfterApLaunch; |
| 65 | extern CONST REGISTER_TABLE ROMDATA F16KbPciWorkaroundTable; |
| 66 | extern CONST REGISTER_TABLE ROMDATA F16KbMsrRegisterTable; |
| 67 | extern CONST REGISTER_TABLE ROMDATA F16KbMsrWorkaroundTable; |
| 68 | extern CONST REGISTER_TABLE ROMDATA F16KbSharedMsrRegisterTable; |
| 69 | extern CONST REGISTER_TABLE ROMDATA F16KbSharedMsrWorkaroundTable; |
| 70 | |
| 71 | /** |
| 72 | * Compute unit and Compute unit primary determination table. |
| 73 | * |
| 74 | * The four fields from the compute unit status hardware register can be used to determine whether |
| 75 | * even number cores are primary or all cores are primary. It can be extended if it is |
| 76 | * decided to have other configs as well. The other logically possible value sets are BitMapMapping, |
| 77 | * but they are currently not supported by the processor. |
| 78 | */ |
| 79 | CONST COMPUTE_UNIT_MAP ROMDATA HtFam16KbComputeUnitMapping[] = |
| 80 | { |
| 81 | {1, 'x', 'x', 1, QuadCoresMapping}, ///< 1 Compute Unit with 4 Cores |
| 82 | {1, 'x', 1, 0, TripleCoresMapping}, ///< 1 Compute Unit with 3 Cores |
| 83 | {1, 1, 0, 0, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores |
| 84 | {1, 0, 0, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 Cores |
| 85 | {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End |
| 86 | }; |
| 87 | |
| 88 | |
| 89 | #if USES_REGISTER_TABLES == TRUE |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 90 | CONST REGISTER_TABLE ROMDATA * CONST F16KbRegisterTables[] = |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 91 | { |
| 92 | #if MODEL_SPECIFIC_PCI == TRUE |
| 93 | &F16KbPciRegisterTableBeforeApLaunch, |
| 94 | &F16KbPciRegisterTableAfterApLaunch, |
| 95 | &F16KbPciWorkaroundTable, |
| 96 | #endif |
| 97 | #if MODEL_SPECIFIC_MSR == TRUE |
| 98 | &F16KbMsrRegisterTable, |
| 99 | &F16KbMsrWorkaroundTable, |
| 100 | &F16KbSharedMsrRegisterTable, |
| 101 | &F16KbSharedMsrWorkaroundTable, |
| 102 | #endif |
| 103 | // the end. |
| 104 | NULL |
| 105 | }; |
| 106 | #endif |
| 107 | |
| 108 | #if USES_REGISTER_TABLES == TRUE |
| 109 | CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F16KbTableEntryTypeDescriptors[] = |
| 110 | { |
| 111 | {MsrRegister, SetRegisterForMsrEntry}, |
| 112 | {PciRegister, SetRegisterForPciEntry}, |
| 113 | {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, |
| 114 | {ProfileFixup, SetRegisterForPerformanceProfileEntry}, |
| 115 | {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, |
| 116 | // End |
| 117 | {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} |
| 118 | }; |
| 119 | #endif |
| 120 | |
| 121 | /** |
| 122 | * Early Init Tables |
| 123 | * |
| 124 | */ |
| 125 | extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesBeforeApLaunch; |
| 126 | extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAfterApLaunch; |
| 127 | extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly; |
| 128 | extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; |
| 129 | extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 130 | extern F_PERFORM_EARLY_INIT_ON_CORE F16KbLoadMicrocodePatchAtEarly; |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 131 | |
| 132 | CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] = |
| 133 | { |
| 134 | {SetRegistersFromTablesBeforeApLaunch, PERFORM_EARLY_ANY_CONDITION}, |
| 135 | {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, |
| 136 | #if OPTION_EARLY_SAMPLES == TRUE |
| 137 | {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, |
| 138 | #endif |
| 139 | {NULL, 0} |
| 140 | }; |
| 141 | |
| 142 | CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitAfterApLaunchOnCoreTable[] = |
| 143 | { |
| 144 | {SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION}, |
| 145 | {F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, |
| 146 | #if OPTION_EARLY_SAMPLES == FALSE |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 147 | {F16KbLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 148 | #endif |
| 149 | {NULL, 0} |
| 150 | }; |
| 151 | |
| 152 | #include "OptionCpuSpecificServicesInstallReset.h" |
| 153 | #define CpuSrvcTableName cpuF16KbServices |
| 154 | |
| 155 | #define CpuSrvcDisablePstate F16DisablePstate |
| 156 | #define CpuSrvcTransitionPstate F16TransitionPstate |
| 157 | #define CpuSrvcGetProcIddMax F16KbGetProcIddMax |
| 158 | #define CpuSrvcGetTscRate F16GetTscRate |
| 159 | #define CpuSrvcGetCurrentNbFrequency F16KbGetCurrentNbFrequency |
| 160 | #define CpuSrvcGetMinMaxNbFrequency F16KbGetMinMaxNbFrequency |
| 161 | #define CpuSrvcGetNbPstateInfo F16KbGetNbPstateInfo |
| 162 | #define CpuSrvcIsNbCofInitNeeded F16GetNbCofVidUpdate |
| 163 | #define CpuSrvcGetNbIddMax F16KbGetNbIddMax |
| 164 | #define CpuSrvcLaunchApCore F16LaunchApCore |
| 165 | #define CpuSrvcGetNumberOfPhysicalCores F16KbGetNumberOfPhysicalCores |
| 166 | #define CpuSrvcGetApMailboxFromHardware F16KbGetApMailboxFromHardware |
| 167 | #define CpuSrvcGetApCoreNumber F16KbGetApCoreNumber |
| 168 | #define CpuSrvcCoreIdPositionInInitialApicId F16CpuAmdCoreIdPositionInInitialApicId |
| 169 | #define CpuSrvcSetWarmResetFlag F16SetAgesaWarmResetFlag |
| 170 | #define CpuSrvcGetWarmResetFlag F16GetAgesaWarmResetFlag |
| 171 | #define CpuSrvcGetMicroCodePatchesStruct GetF16KbMicroCodePatchesStruct |
| 172 | #define CpuSrvcGetMicrocodeEquivalenceTable GetF16KbMicrocodeEquivalenceTable |
| 173 | #define CpuSrvcGetCacheInfo GetF16CacheInfo |
| 174 | #define CpuSrvcGetSysPmTableStruct GetF16KbSysPmTable |
| 175 | #define CpuSrvcGetWheaInitData GetF16WheaInitData |
| 176 | #define CpuSrvcIsNbPstateEnabled F16KbIsNbPstateEnabled |
| 177 | #define CpuSrvcRegisterTableList (REGISTER_TABLE **) F16KbRegisterTables |
| 178 | #define CpuSrvcTableEntryTypeDescriptors (TABLE_ENTRY_TYPE_DESCRIPTOR *) F16KbTableEntryTypeDescriptors |
| 179 | #define CpuSrvcComputeUnitMap (COMPUTE_UNIT_MAP *) &HtFam16KbComputeUnitMapping |
| 180 | #define CpuSrvcInitCacheDisabled InitCacheEnabled |
| 181 | #define CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable GetF16KbEarlyInitBeforeApLaunchOnCoreTable |
| 182 | #define CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable GetF16KbEarlyInitAfterApLaunchOnCoreTable |
| 183 | #define CpuSrvcPatchLoaderIsSharedByCU FALSE |
| 184 | |
| 185 | #include "OptionCpuSpecificServicesInstall.h" |
| 186 | INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName); |
| 187 | |
| 188 | #define KB_SOCKETS 1 |
| 189 | #define KB_MODULES 1 |
| 190 | #define KB_RECOVERY_SOCKETS 1 |
| 191 | #define KB_RECOVERY_MODULES 1 |
| 192 | extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF16KbLogicalIdAndRev; |
| 193 | #define OPT_F16_KB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF16KbLogicalIdAndRev, |
| 194 | #ifndef ADVCFG_PLATFORM_SOCKETS |
| 195 | #define ADVCFG_PLATFORM_SOCKETS KB_SOCKETS |
| 196 | #else |
| 197 | #if ADVCFG_PLATFORM_SOCKETS < KB_SOCKETS |
| 198 | #undef ADVCFG_PLATFORM_SOCKETS |
| 199 | #define ADVCFG_PLATFORM_SOCKETS KB_SOCKETS |
| 200 | #endif |
| 201 | #endif |
| 202 | #ifndef ADVCFG_PLATFORM_MODULES |
| 203 | #define ADVCFG_PLATFORM_MODULES KB_MODULES |
| 204 | #else |
| 205 | #if ADVCFG_PLATFORM_MODULES < KB_MODULES |
| 206 | #undef ADVCFG_PLATFORM_MODULES |
| 207 | #define ADVCFG_PLATFORM_MODULES KB_MODULES |
| 208 | #endif |
| 209 | #endif |
| 210 | |
Kyösti Mälkki | d136b8e | 2017-08-31 16:58:27 +0300 | [diff] [blame] | 211 | #if (AGESA_ENTRY_INIT_EARLY == TRUE) |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 212 | #define F16_KB_UCODE_7000 |
| 213 | #define F16_KB_UCODE_7001 |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 214 | |
| 215 | #if AGESA_ENTRY_INIT_EARLY == TRUE |
| 216 | #if OPTION_EARLY_SAMPLES == TRUE |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 217 | extern CONST UINT8 ROMDATA CpuF16KbId7000MicrocodePatch[]; |
| 218 | #undef F16_KB_UCODE_7000 |
| 219 | #define F16_KB_UCODE_7000 CpuF16KbId7000MicrocodePatch, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 220 | #endif |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 221 | extern CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch[]; |
| 222 | #undef F16_KB_UCODE_7001 |
| 223 | #define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch, |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 224 | #endif |
| 225 | |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 226 | CONST UINT8 ROMDATA * CONST CpuF16KbMicroCodePatchArray[] = |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 227 | { |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 228 | F16_KB_UCODE_7001 |
| 229 | F16_KB_UCODE_7000 |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 230 | NULL |
| 231 | }; |
| 232 | |
| 233 | CONST UINT8 ROMDATA CpuF16KbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF16KbMicroCodePatchArray) / sizeof (CpuF16KbMicroCodePatchArray[0])) - 1); |
| 234 | #endif |
| 235 | |
| 236 | #define OPT_F16_KB_CPU {AMD_FAMILY_16_KB, &cpuF16KbServices}, |
| 237 | |
| 238 | #else // OPTION_FAMILY16H_KB == TRUE |
| 239 | #define OPT_F16_KB_CPU |
| 240 | #define OPT_F16_KB_ID |
| 241 | #endif // OPTION_FAMILY16H_KB == TRUE |
| 242 | #else // defined (OPTION_FAMILY16H_KB) |
| 243 | #define OPT_F16_KB_CPU |
| 244 | #define OPT_F16_KB_ID |
| 245 | #endif // defined (OPTION_FAMILY16H_KB) |
| 246 | |
| 247 | |
| 248 | /* |
| 249 | * Install unknown family 16h support |
| 250 | */ |
| 251 | |
| 252 | |
| 253 | #if USES_REGISTER_TABLES == TRUE |
| 254 | extern CONST REGISTER_TABLE ROMDATA F16PciUnknownRegisterTable; |
| 255 | extern CONST REGISTER_TABLE ROMDATA F16MsrUnknownRegisterTable; |
Arthur Heymans | b80de18 | 2022-05-16 15:29:53 +0200 | [diff] [blame^] | 256 | CONST REGISTER_TABLE ROMDATA * CONST F16UnknownRegisterTables[] = |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 257 | { |
| 258 | &F16PciUnknownRegisterTable, |
| 259 | &F16MsrUnknownRegisterTable |
| 260 | // the end. |
| 261 | }; |
| 262 | #endif |
| 263 | |
| 264 | #if USES_REGISTER_TABLES == TRUE |
| 265 | CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F16UnknownTableEntryTypeDescriptors[] = |
| 266 | { |
| 267 | {MsrRegister, SetRegisterForMsrEntry}, |
| 268 | {PciRegister, SetRegisterForPciEntry}, |
| 269 | // End |
| 270 | {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} |
| 271 | }; |
| 272 | #endif |
| 273 | |
| 274 | |
| 275 | |
| 276 | #include "OptionCpuSpecificServicesInstallReset.h" |
| 277 | #define CpuSrvcTableName cpuF16UnknownServices |
| 278 | |
| 279 | #define CpuSrvcDisablePstate F16DisablePstate |
| 280 | #define CpuSrvcTransitionPstate F16TransitionPstate |
| 281 | #define CpuSrvcGetTscRate F16GetTscRate |
| 282 | #define CpuSrvcLaunchApCore F16LaunchApCore |
| 283 | #define CpuSrvcCoreIdPositionInInitialApicId F16CpuAmdCoreIdPositionInInitialApicId |
| 284 | #define CpuSrvcSetWarmResetFlag F16SetAgesaWarmResetFlag |
| 285 | #define CpuSrvcGetWarmResetFlag F16GetAgesaWarmResetFlag |
| 286 | #define CpuSrvcGetMicroCodePatchesStruct GetEmptyArray |
| 287 | #define CpuSrvcGetMicrocodeEquivalenceTable GetEmptyArray |
| 288 | #define CpuSrvcGetWheaInitData GetF16WheaInitData |
| 289 | #define CpuSrvcIsNbPstateEnabled F16IsNbPstateEnabled |
| 290 | #define CpuSrvcRegisterTableList (REGISTER_TABLE **) F16UnknownRegisterTables |
| 291 | #define CpuSrvcTableEntryTypeDescriptors (TABLE_ENTRY_TYPE_DESCRIPTOR *) F16UnknownTableEntryTypeDescriptors |
| 292 | #define CpuSrvcInitCacheDisabled InitCacheEnabled |
| 293 | #define CpuSrvcPatchLoaderIsSharedByCU FALSE |
| 294 | |
| 295 | #include "OptionCpuSpecificServicesInstall.h" |
| 296 | INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName); |
| 297 | |
| 298 | // Family 16h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate. |
| 299 | |
| 300 | #if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull) |
| 301 | |
| 302 | #undef FAMILY_MMIO_BASE_MASK |
| 303 | |
| 304 | #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull) |
| 305 | |
| 306 | #endif |
| 307 | |
| 308 | |
| 309 | |
| 310 | #undef OPT_F16_ID_TABLE |
| 311 | |
| 312 | #define OPT_F16_ID_TABLE {0x16, {AMD_FAMILY_16, AMD_F16_UNKNOWN}, F16LogicalIdTable, (sizeof (F16LogicalIdTable) / sizeof (F16LogicalIdTable[0]))}, |
| 313 | |
| 314 | #define OPT_F16_UNKNOWN_CPU {AMD_FAMILY_16, &cpuF16UnknownServices}, |
| 315 | |
| 316 | |
| 317 | #undef OPT_F16_TABLE |
| 318 | |
| 319 | #define OPT_F16_TABLE OPT_F16_KB_CPU OPT_F16_UNKNOWN_CPU |
| 320 | |
| 321 | |
| 322 | |
| 323 | CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F16LogicalIdTable[] = |
| 324 | |
| 325 | { |
| 326 | |
| 327 | OPT_F16_KB_ID |
| 328 | |
| 329 | }; |
| 330 | |
| 331 | |
| 332 | #endif // _OPTION_FAMILY_16H_INSTALL_H_ |