Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
| 25 | #include <arch/byteorder.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <arch/romcc_io.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <device/pnp_def.h> |
| 30 | #include <cpu/x86/lapic.h> |
| 31 | #include <pc80/mc146818rtc.h> |
| 32 | #include <cbmem.h> |
| 33 | #include <console/console.h> |
| 34 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 35 | #include "northbridge/intel/sandybridge/raminit.h" |
| 36 | #include "southbridge/intel/bd82x6x/pch.h" |
| 37 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 38 | #include <arch/cpu.h> |
| 39 | #include <cpu/x86/bist.h> |
| 40 | #include <cpu/x86/msr.h> |
| 41 | #include "gpio.h" |
| 42 | #if CONFIG_CHROMEOS |
| 43 | #include <vendorcode/google/chromeos/chromeos.h> |
| 44 | #endif |
| 45 | #include <cbfs.h> |
| 46 | #include <ec/quanta/it8518/ec.h> |
| 47 | #include "ec.h" |
| 48 | #include "onboard.h" |
| 49 | |
| 50 | static void pch_enable_lpc(void) |
| 51 | { |
| 52 | /* |
| 53 | * Enable: |
| 54 | * EC Decode Range Port62/66 |
| 55 | * SuperIO Port2E/2F |
| 56 | * PS/2 Keyboard/Mouse Port60/64 |
| 57 | * FDD Port3F0h-3F5h and Port3F7h |
| 58 | */ |
| 59 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | |
| 60 | CNF1_LPC_EN | FDD_LPC_EN); |
| 61 | |
| 62 | /* Stout EC Decode Range Port68/6C */ |
| 63 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001)); |
| 64 | } |
| 65 | |
| 66 | static void rcba_config(void) |
| 67 | { |
| 68 | u32 reg32; |
| 69 | |
| 70 | /* |
| 71 | * GFX INTA -> PIRQA (MSI) |
| 72 | * D20IP_XHCI XHCI INTA -> PIRQD (MSI) |
| 73 | * D26IP_E2P EHCI #2 INTA -> PIRQF |
| 74 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 75 | * D28IP_P2IP WLAN INTA -> PIRQD |
| 76 | * D28IP_P3IP Card Reader INTB -> PIRQE |
| 77 | * D28IP_P6IP LAN INTC -> PIRQB |
| 78 | * D29IP_E1P EHCI #1 INTA -> PIRQD |
| 79 | * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| 80 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 81 | */ |
| 82 | |
| 83 | /* Device interrupt pin register (board specific) */ |
| 84 | RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 85 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 86 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 87 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 88 | RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | |
| 89 | (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | |
| 90 | (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | |
| 91 | (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); |
| 92 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 93 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 94 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 95 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 96 | RCBA32(D20IP) = (INTA << D20IP_XHCIIP); |
| 97 | |
| 98 | /* Device interrupt route registers */ |
| 99 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 100 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 101 | DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); |
| 102 | DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 103 | DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); |
| 104 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 105 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 106 | DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 107 | |
| 108 | /* Enable IOAPIC (generic) */ |
| 109 | RCBA16(OIC) = 0x0100; |
| 110 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 111 | (void) RCBA16(OIC); |
| 112 | |
| 113 | /* Disable unused devices (board specific) */ |
| 114 | reg32 = RCBA32(FD); |
| 115 | reg32 |= PCH_DISABLE_ALWAYS; |
| 116 | /* Disable PCI bridge so MRC does not probe this bus */ |
| 117 | reg32 |= PCH_DISABLE_P2P; |
| 118 | RCBA32(FD) = reg32; |
| 119 | } |
| 120 | |
| 121 | // FIXME, this function is generic code that should go to sb/... or |
| 122 | // nb/../early_init.c |
| 123 | static void early_pch_init(void) |
| 124 | { |
| 125 | // Nothing to do for stout |
| 126 | } |
| 127 | |
| 128 | /* |
| 129 | * The Stout EC needs to be reset to RW mode. It is important that |
| 130 | * the RTC_PWR_STS is not set until ramstage EC init. |
| 131 | */ |
| 132 | static void early_ec_init(void) |
| 133 | { |
| 134 | u8 ec_status = ec_read(EC_STATUS_REG); |
| 135 | int rec_mode = get_recovery_mode_switch(); |
| 136 | |
| 137 | if (((ec_status & 0x3) == EC_IN_RO_MODE) || |
| 138 | ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) { |
| 139 | |
| 140 | printk(BIOS_DEBUG, "EC Cold Boot Detected\n"); |
| 141 | if (!rec_mode) { |
| 142 | /* |
| 143 | * Tell EC to exit RO mode |
| 144 | */ |
| 145 | printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n"); |
| 146 | ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK); |
| 147 | die("wait for ec to reset"); |
| 148 | } |
| 149 | } else { |
| 150 | printk(BIOS_DEBUG, "EC Warm Boot Detected\n"); |
| 151 | ec_write_cmd(EC_CMD_WARM_RESET); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | void main(unsigned long bist) |
| 156 | { |
| 157 | int boot_mode = 0; |
| 158 | int cbmem_was_initted; |
| 159 | u32 pm1_cnt; |
| 160 | u16 pm1_sts; |
| 161 | |
| 162 | #if CONFIG_COLLECT_TIMESTAMPS |
| 163 | tsc_t start_romstage_time; |
| 164 | tsc_t before_dram_time; |
| 165 | tsc_t after_dram_time; |
| 166 | tsc_t base_time = { |
| 167 | .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), |
| 168 | .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) |
| 169 | }; |
| 170 | #endif |
| 171 | struct pei_data pei_data = { |
| 172 | pei_version: PEI_VERSION, |
| 173 | mchbar: DEFAULT_MCHBAR, |
| 174 | dmibar: DEFAULT_DMIBAR, |
| 175 | epbar: DEFAULT_EPBAR, |
| 176 | pciexbar: CONFIG_MMCONF_BASE_ADDRESS, |
| 177 | smbusbar: SMBUS_IO_BASE, |
| 178 | wdbbar: 0x4000000, |
| 179 | wdbsize: 0x1000, |
| 180 | hpet_address: CONFIG_HPET_ADDRESS, |
| 181 | rcba: DEFAULT_RCBABASE, |
| 182 | pmbase: DEFAULT_PMBASE, |
| 183 | gpiobase: DEFAULT_GPIOBASE, |
| 184 | thermalbase: 0xfed08000, |
| 185 | system_type: 0, // 0 Mobile, 1 Desktop/Server |
| 186 | tseg_size: CONFIG_SMM_TSEG_SIZE, |
| 187 | spd_addresses: { 0xA0, 0x00,0xA4,0x00 }, |
| 188 | ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, |
| 189 | ec_present: 1, |
| 190 | // 0 = leave channel enabled |
| 191 | // 1 = disable dimm 0 on channel |
| 192 | // 2 = disable dimm 1 on channel |
| 193 | // 3 = disable dimm 0+1 on channel |
| 194 | dimm_channel0_disabled: 2, |
| 195 | dimm_channel1_disabled: 2, |
| 196 | max_ddr3_freq: 1600, |
| 197 | usb_port_config: { |
| 198 | /* enabled usb oc pin length */ |
| 199 | { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ |
| 200 | { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ |
| 201 | { 0, 1, 0x0000 }, /* P2: Empty */ |
| 202 | { 1, 1, 0x0040 }, /* P3: Camera (no OC) */ |
| 203 | { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */ |
| 204 | { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */ |
| 205 | { 0, 1, 0x0000 }, /* P6: Empty */ |
| 206 | { 0, 1, 0x0000 }, /* P7: Empty */ |
| 207 | { 0, 5, 0x0000 }, /* P8: Empty */ |
| 208 | { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */ |
| 209 | { 0, 5, 0x0000 }, /* P10: Empty */ |
| 210 | { 0, 5, 0x0000 }, /* P11: Empty */ |
| 211 | { 0, 5, 0x0000 }, /* P12: Empty */ |
| 212 | { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ |
| 213 | }, |
| 214 | usb3: { |
| 215 | mode: XHCI_MODE, |
| 216 | hs_port_switch_mask: XHCI_PORTS, |
| 217 | preboot_support: XHCI_PREBOOT, |
| 218 | xhci_streams: XHCI_STREAMS, |
| 219 | }, |
| 220 | }; |
| 221 | |
| 222 | #if CONFIG_COLLECT_TIMESTAMPS |
| 223 | start_romstage_time = rdtsc(); |
| 224 | #endif |
| 225 | |
| 226 | if (bist == 0) |
| 227 | enable_lapic(); |
| 228 | |
| 229 | pch_enable_lpc(); |
| 230 | |
| 231 | /* Enable GPIOs */ |
| 232 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 233 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 234 | setup_pch_gpios(&stout_gpio_map); |
| 235 | |
| 236 | /* Initialize console device(s) */ |
| 237 | console_init(); |
| 238 | |
| 239 | /* Halt if there was a built in self test failure */ |
| 240 | report_bist_failure(bist); |
| 241 | |
| 242 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 243 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 244 | boot_mode = 1; |
| 245 | |
| 246 | /* System is not happy after keyboard reset... */ |
| 247 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 248 | outb(0x6, 0xcf9); |
| 249 | hlt(); |
| 250 | } |
| 251 | |
| 252 | |
| 253 | /* Perform some early chipset initialization required |
| 254 | * before RAM initialization can work |
| 255 | */ |
| 256 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 257 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 258 | |
| 259 | /* Check PM1_STS[15] to see if we are waking from Sx */ |
| 260 | pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); |
| 261 | |
| 262 | /* Read PM1_CNT[12:10] to determine which Sx state */ |
| 263 | pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); |
| 264 | |
| 265 | if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { |
| 266 | #if CONFIG_HAVE_ACPI_RESUME |
| 267 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
| 268 | boot_mode = 2; |
| 269 | /* Clear SLP_TYPE. This will break stage2 but |
| 270 | * we care for that when we get there. |
| 271 | */ |
| 272 | outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); |
| 273 | #else |
| 274 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
| 275 | #endif |
| 276 | } |
| 277 | |
| 278 | /* Do ec reset as early as possible, but skip it on S3 resume */ |
| 279 | if (boot_mode < 2) |
| 280 | early_ec_init(); |
| 281 | |
| 282 | post_code(0x38); |
| 283 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 284 | enable_smbus(); |
| 285 | |
| 286 | /* Prepare USB controller early in S3 resume */ |
| 287 | if (boot_mode == 2) |
| 288 | enable_usb_bar(); |
| 289 | |
| 290 | post_code(0x39); |
| 291 | |
| 292 | post_code(0x3a); |
| 293 | pei_data.boot_mode = boot_mode; |
| 294 | #if CONFIG_COLLECT_TIMESTAMPS |
| 295 | before_dram_time = rdtsc(); |
| 296 | #endif |
| 297 | sdram_initialize(&pei_data); |
| 298 | |
| 299 | #if CONFIG_COLLECT_TIMESTAMPS |
| 300 | after_dram_time = rdtsc(); |
| 301 | #endif |
| 302 | post_code(0x3b); |
| 303 | /* Perform some initialization that must run before stage2 */ |
| 304 | early_pch_init(); |
| 305 | post_code(0x3c); |
| 306 | |
| 307 | rcba_config(); |
| 308 | post_code(0x3d); |
| 309 | |
| 310 | quick_ram_check(); |
| 311 | post_code(0x3e); |
| 312 | |
| 313 | MCHBAR16(SSKPD) = 0xCAFE; |
| 314 | #if CONFIG_EARLY_CBMEM_INIT |
| 315 | cbmem_was_initted = !cbmem_initialize(); |
| 316 | #else |
| 317 | cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() |
| 318 | - HIGH_MEMORY_SIZE)); |
| 319 | #endif |
| 320 | |
| 321 | #if CONFIG_HAVE_ACPI_RESUME |
| 322 | /* If there is no high memory area, we didn't boot before, so |
| 323 | * this is not a resume. In that case we just create the cbmem toc. |
| 324 | */ |
| 325 | |
| 326 | *(u32 *)CBMEM_BOOT_MODE = 0; |
| 327 | *(u32 *)CBMEM_RESUME_BACKUP = 0; |
| 328 | |
| 329 | if ((boot_mode == 2) && cbmem_was_initted) { |
| 330 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 331 | if (resume_backup_memory) { |
| 332 | *(u32 *)CBMEM_BOOT_MODE = boot_mode; |
| 333 | *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; |
| 334 | } |
| 335 | /* Magic for S3 resume */ |
| 336 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 337 | } else if (boot_mode == 2) { |
| 338 | /* Failed S3 resume, reset to come up cleanly */ |
| 339 | outb(0x6, 0xcf9); |
| 340 | hlt(); |
| 341 | } else { |
| 342 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 343 | } |
| 344 | #endif |
| 345 | post_code(0x3f); |
| 346 | #if CONFIG_CHROMEOS |
| 347 | init_chromeos(boot_mode); |
| 348 | #endif |
| 349 | #if CONFIG_COLLECT_TIMESTAMPS |
| 350 | timestamp_init(base_time); |
| 351 | timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); |
| 352 | timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); |
| 353 | timestamp_add(TS_AFTER_INITRAM, after_dram_time ); |
| 354 | timestamp_add_now(TS_END_ROMSTAGE); |
| 355 | #endif |
| 356 | #if CONFIG_CONSOLE_CBMEM |
| 357 | /* Keep this the last thing this function does. */ |
| 358 | cbmemc_reinit(); |
| 359 | #endif |
| 360 | } |