Martin Roth | 239b5df | 2022-07-26 22:18:26 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 3 | #ifndef RESET_H |
| 4 | #define RESET_H |
Eric Biederman | 30e143a | 2003-09-01 23:45:32 +0000 | [diff] [blame] | 5 | |
Nico Huber | 4f32b64 | 2018-10-05 23:40:21 +0200 | [diff] [blame] | 6 | /* |
| 7 | * Generic board reset function. Call from common code that |
| 8 | * wants to trigger a reset. |
| 9 | */ |
| 10 | __noreturn void board_reset(void); |
| 11 | /* |
| 12 | * SoC or board specific implementation of the board reset. |
| 13 | * |
| 14 | * Implementations shall meet the following criteria: |
| 15 | * |
| 16 | * o For vboot support, the TPM MUST be reset. |
| 17 | * |
| 18 | * o All SoC/chipset blocks SHOULD be reset except for those |
| 19 | * that are intentionally meant to survive reset (e.g. tomb- |
| 20 | * stone registers and that sort of stuff). |
| 21 | * |
| 22 | * o All external SoC pins SHOULD return to power-on reset values. |
| 23 | * |
| 24 | * o The CPU MUST resume execution from power-on reset vector |
| 25 | * (same as cold boot). |
| 26 | * |
| 27 | * o Other board components (e.g. PCI, SDIO and stuff) SHOULD |
| 28 | * be reset. |
| 29 | * |
| 30 | * o USB SHOULD be power-cycled. |
| 31 | * |
| 32 | * o Board components that are intended to be fully independent |
| 33 | * from SoC (e.g. EC and EC-attached devices, the Cr50 on |
| 34 | * Chromebooks) SHOULD NOT be reset. |
| 35 | * |
| 36 | * General recommendations: |
| 37 | * |
| 38 | * o DRAM SHOULD NOT lose power if possible. |
| 39 | * |
| 40 | * o Reset time SHOULD be minimized |
| 41 | */ |
| 42 | void do_board_reset(void); |
Julius Werner | 01f9aa5 | 2017-05-18 16:03:26 -0700 | [diff] [blame] | 43 | |
Eric Biederman | 30e143a | 2003-09-01 23:45:32 +0000 | [diff] [blame] | 44 | #endif |