Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 2 | |
Angel Pons | b6d7a12 | 2021-02-19 18:37:37 +0100 | [diff] [blame^] | 3 | #include <console/console.h> |
| 4 | #include <cpu/intel/em64t101_save_state.h> |
| 5 | #include <cpu/intel/smm_reloc.h> |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 6 | #include <cpu/x86/mp.h> |
| 7 | #include <cpu/x86/msr.h> |
| 8 | #include <cpu/x86/mtrr.h> |
| 9 | #include <cpu/x86/smm.h> |
Angel Pons | b6d7a12 | 2021-02-19 18:37:37 +0100 | [diff] [blame^] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ops.h> |
Elyes HAOUAS | dda17fa | 2019-10-27 13:09:37 +0100 | [diff] [blame] | 13 | #include <smp/node.h> |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 14 | #include <soc/cpu.h> |
| 15 | #include <soc/msr.h> |
| 16 | #include <soc/pci_devs.h> |
Angel Pons | b6d7a12 | 2021-02-19 18:37:37 +0100 | [diff] [blame^] | 17 | #include <soc/soc_chip.h> |
| 18 | #include <string.h> |
| 19 | #include <types.h> |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 20 | |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 21 | static void update_save_state(int cpu, uintptr_t curr_smbase, |
| 22 | uintptr_t staggered_smbase, |
| 23 | struct smm_relocation_params *relo_params) |
| 24 | { |
| 25 | u32 smbase; |
| 26 | u32 iedbase; |
| 27 | |
| 28 | /* |
| 29 | * The relocated handler runs with all CPUs concurrently. Therefore |
| 30 | * stagger the entry points adjusting SMBASE downwards by save state |
| 31 | * size * CPU num. |
| 32 | */ |
| 33 | smbase = staggered_smbase; |
| 34 | iedbase = relo_params->ied_base; |
| 35 | |
| 36 | printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", |
| 37 | smbase, iedbase); |
| 38 | |
| 39 | /* |
| 40 | * All threads need to set IEDBASE and SMBASE to the relocated |
| 41 | * handler region. However, the save state location depends on the |
| 42 | * smm_save_state_in_msrs field in the relocation parameters. If |
| 43 | * smm_save_state_in_msrs is non-zero then the CPUs are relocating |
| 44 | * the SMM handler in parallel, and each CPUs save state area is |
| 45 | * located in their respective MSR space. If smm_save_state_in_msrs |
| 46 | * is zero then the SMM relocation is happening serially so the |
| 47 | * save state is at the same default location for all CPUs. |
| 48 | */ |
| 49 | if (relo_params->smm_save_state_in_msrs) { |
| 50 | msr_t smbase_msr; |
| 51 | msr_t iedbase_msr; |
| 52 | |
| 53 | smbase_msr.lo = smbase; |
| 54 | smbase_msr.hi = 0; |
| 55 | |
| 56 | /* |
| 57 | * According the BWG the IEDBASE MSR is in bits 63:32. It's |
| 58 | * not clear why it differs from the SMBASE MSR. |
| 59 | */ |
| 60 | iedbase_msr.lo = 0; |
| 61 | iedbase_msr.hi = iedbase; |
| 62 | |
| 63 | wrmsr(SMBASE_MSR, smbase_msr); |
| 64 | wrmsr(IEDBASE_MSR, iedbase_msr); |
| 65 | } else { |
| 66 | em64t101_smm_state_save_area_t *save_state; |
| 67 | |
| 68 | save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - |
| 69 | sizeof(*save_state)); |
| 70 | |
| 71 | save_state->smbase = smbase; |
| 72 | save_state->iedbase = iedbase; |
| 73 | } |
| 74 | } |
| 75 | |
| 76 | /* Returns 1 if SMM MSR save state was set. */ |
| 77 | static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) |
| 78 | { |
| 79 | msr_t smm_mca_cap; |
| 80 | |
| 81 | smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); |
| 82 | if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { |
| 83 | msr_t smm_feature_control; |
| 84 | |
| 85 | smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); |
| 86 | smm_feature_control.hi = 0; |
| 87 | smm_feature_control.lo |= SMM_CPU_SAVE_EN; |
| 88 | wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); |
| 89 | relo_params->smm_save_state_in_msrs = 1; |
| 90 | } |
| 91 | return relo_params->smm_save_state_in_msrs; |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * The relocation work is actually performed in SMM context, but the code |
| 96 | * resides in the ramstage module. This occurs by trampolining from the default |
| 97 | * SMRAM entry point to here. |
| 98 | */ |
| 99 | void smm_relocation_handler(int cpu, uintptr_t curr_smbase, |
| 100 | uintptr_t staggered_smbase) |
| 101 | { |
| 102 | msr_t mtrr_cap; |
| 103 | struct smm_relocation_params *relo_params = &smm_reloc_params; |
| 104 | |
| 105 | printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); |
| 106 | |
| 107 | /* |
| 108 | * Determine if the processor supports saving state in MSRs. If so, |
| 109 | * enable it before the non-BSPs run so that SMM relocation can occur |
| 110 | * in parallel in the non-BSP CPUs. |
| 111 | */ |
| 112 | if (cpu == 0) { |
| 113 | /* |
| 114 | * If smm_save_state_in_msrs is 1 then that means this is the |
| 115 | * 2nd time through the relocation handler for the BSP. |
| 116 | * Parallel SMM handler relocation is taking place. However, |
| 117 | * it is desired to access other CPUs save state in the real |
| 118 | * SMM handler. Therefore, disable the SMM save state in MSRs |
| 119 | * feature. |
| 120 | */ |
| 121 | if (relo_params->smm_save_state_in_msrs) { |
| 122 | msr_t smm_feature_control; |
| 123 | |
| 124 | smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); |
| 125 | smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; |
| 126 | wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); |
| 127 | } else if (bsp_setup_msr_save_state(relo_params)) |
| 128 | /* |
| 129 | * Just return from relocation handler if MSR save |
| 130 | * state is enabled. In that case the BSP will come |
| 131 | * back into the relocation handler to setup the new |
| 132 | * SMBASE as well disabling SMM save state in MSRs. |
| 133 | */ |
| 134 | return; |
| 135 | } |
| 136 | |
| 137 | /* Make appropriate changes to the save state map. */ |
| 138 | update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); |
| 139 | |
Kyösti Mälkki | 621142a | 2019-08-11 09:24:30 +0300 | [diff] [blame] | 140 | /* Write SMRR MSRs based on indicated support. */ |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 141 | mtrr_cap = rdmsr(MTRR_CAP_MSR); |
| 142 | if (mtrr_cap.lo & SMRR_SUPPORTED) |
| 143 | write_smrr(relo_params); |
| 144 | } |
| 145 | |
Kyösti Mälkki | d788663 | 2019-08-05 11:35:27 +0300 | [diff] [blame] | 146 | static void fill_in_relocation_params(struct smm_relocation_params *params) |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 147 | { |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 148 | uintptr_t tseg_base; |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 149 | size_t tseg_size; |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 150 | /* All range registers are aligned to 4KiB */ |
| 151 | const u32 rmask = ~(4 * KiB - 1); |
| 152 | |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 153 | smm_region(&tseg_base, &tseg_size); |
Benjamin Doron | 448ecc0 | 2020-10-14 05:29:09 +0000 | [diff] [blame] | 154 | |
| 155 | if (!IS_ALIGNED(tseg_base, tseg_size)) { |
| 156 | printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n"); |
| 157 | return; |
| 158 | } |
| 159 | |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 160 | smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 161 | |
| 162 | /* SMRR has 32-bits of valid address aligned to 4KiB. */ |
Kyösti Mälkki | 41d9b65 | 2019-08-05 22:00:08 +0300 | [diff] [blame] | 163 | params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 164 | params->smrr_base.hi = 0; |
Kyösti Mälkki | 41d9b65 | 2019-08-05 22:00:08 +0300 | [diff] [blame] | 165 | params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 166 | params->smrr_mask.hi = 0; |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | static void setup_ied_area(struct smm_relocation_params *params) |
| 170 | { |
| 171 | char *ied_base; |
| 172 | |
| 173 | struct ied_header ied = { |
| 174 | .signature = "INTEL RSVD", |
| 175 | .size = params->ied_size, |
| 176 | .reserved = {0}, |
| 177 | }; |
| 178 | |
| 179 | ied_base = (void *)params->ied_base; |
| 180 | |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 181 | printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); |
| 182 | printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 183 | |
| 184 | /* Place IED header at IEDBASE. */ |
| 185 | memcpy(ied_base, &ied, sizeof(ied)); |
| 186 | |
| 187 | /* Zero out 32KiB at IEDBASE + 1MiB */ |
| 188 | memset(ied_base + 1 * MiB, 0, 32 * KiB); |
| 189 | } |
| 190 | |
| 191 | void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 192 | size_t *smm_save_state_size) |
| 193 | { |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 194 | printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); |
| 195 | |
Kyösti Mälkki | d788663 | 2019-08-05 11:35:27 +0300 | [diff] [blame] | 196 | fill_in_relocation_params(&smm_reloc_params); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 197 | |
Kyösti Mälkki | 2e3aff8 | 2019-08-05 12:49:09 +0300 | [diff] [blame] | 198 | smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); |
| 199 | |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 200 | if (smm_reloc_params.ied_size) |
| 201 | setup_ied_area(&smm_reloc_params); |
| 202 | |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 203 | *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); |
| 204 | } |
| 205 | |
| 206 | void smm_initialize(void) |
| 207 | { |
| 208 | /* Clear the SMM state in the southbridge. */ |
| 209 | smm_southbridge_clear_state(); |
| 210 | |
| 211 | /* |
| 212 | * Run the relocation handler for on the BSP to check and set up |
| 213 | * parallel SMM relocation. |
| 214 | */ |
| 215 | smm_initiate_relocation(); |
| 216 | |
| 217 | if (smm_reloc_params.smm_save_state_in_msrs) |
| 218 | printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); |
| 219 | } |
| 220 | |
| 221 | void smm_relocate(void) |
| 222 | { |
| 223 | /* |
| 224 | * If smm_save_state_in_msrs is non-zero then parallel SMM relocation |
| 225 | * shall take place. Run the relocation handler a second time on the |
| 226 | * BSP to do * the final move. For APs, a relocation handler always |
| 227 | * needs to be run. |
| 228 | */ |
| 229 | if (smm_reloc_params.smm_save_state_in_msrs) |
| 230 | smm_initiate_relocation_parallel(); |
| 231 | else if (!boot_cpu()) |
| 232 | smm_initiate_relocation(); |
| 233 | } |