| Karthikeyan Ramasubramanian | c2f6f35 | 2021-09-10 12:03:30 -0600 | [diff] [blame] | 1 | config PSP_VERSTAGE_CCP_DMA |
| 2 | bool |
| 3 | default n |
| 4 | help |
| 5 | Configure PSP Verstage to use Crypto Co-processor (CCP) DMA while |
| 6 | accessing the boot device. Select it on platforms which supports |
| 7 | using CCP DMA to access the boot device. |
| Rob Barnes | b35acf9 | 2021-11-02 17:47:47 -0600 | [diff] [blame] | 8 | |
| Rob Barnes | 3437a6f | 2021-12-10 14:28:21 -0700 | [diff] [blame] | 9 | config PSP_S0I3_RESUME_VERSTAGE |
| 10 | bool "S0i3 resume verstage" |
| 11 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 12 | default n |
| 13 | help |
| 14 | Select this item to enable running verstage during S0i3 resume. |
| 15 | |
| Rob Barnes | b35acf9 | 2021-11-02 17:47:47 -0600 | [diff] [blame] | 16 | config PSP_INIT_TPM_ON_S0I3_RESUME |
| 17 | bool |
| Rob Barnes | 3437a6f | 2021-12-10 14:28:21 -0700 | [diff] [blame] | 18 | depends on TPM2 && PSP_S0I3_RESUME_VERSTAGE |
| 19 | default PSP_S0I3_RESUME_VERSTAGE |
| Rob Barnes | b35acf9 | 2021-11-02 17:47:47 -0600 | [diff] [blame] | 20 | help |
| 21 | If the TPM is reset while in S0i3, it must be reinitialized |
| 22 | during s0i3 resume. This must be performed in PSP verstage since |
| 23 | coreboot is otherwise not involved with s0i3 resume. |
| Karthikeyan Ramasubramanian | e3eedf7 | 2022-07-14 15:37:07 -0600 | [diff] [blame] | 24 | |
| 25 | config PSP_SUPPORTS_EFS2_RELATIVE_ADDR |
| 26 | bool |
| 27 | default n |
| 28 | help |
| 29 | On SoCs where PSP uses A/B recovery layout, PSP support relative addressing |
| 30 | from the start of the SPI ROM. Enable this config on SoCs where PSP supports |
| 31 | relative addressing so that PSP verstage can pass the offset. |
| Karthikeyan Ramasubramanian | bb31562 | 2022-08-25 15:53:27 -0600 | [diff] [blame] | 32 | |
| 33 | config SEPARATE_SIGNED_PSPFW |
| 34 | def_bool n |
| 35 | help |
| 36 | Put signed AMD/PSP firmwares outside FW_MAIN_[AB] so vboot doesn't verify them, |
| 37 | and rely on PSP's verification. |
| Karthikeyan Ramasubramanian | 204a4e6 | 2023-10-16 21:08:57 +0000 | [diff] [blame] | 38 | |
| 39 | config PSP_VERSTAGE_STACK_IS_MAPPED |
| 40 | bool |
| 41 | default y if SOC_AMD_PICASSO |
| 42 | default n |
| 43 | help |
| 44 | This configuration indicates whether the PSP Verstage stack is mapped to a virtual |
| 45 | address space. This has been the case so far only in Picasso SoC. |
| Karthikeyan Ramasubramanian | b6ab7ba | 2023-11-20 23:34:22 +0000 | [diff] [blame^] | 46 | |
| 47 | config PSP_VERSTAGE_MAP_ENTIRE_SPIROM |
| 48 | bool |
| 49 | default y if SOC_AMD_CEZANNE |
| 50 | default n |
| 51 | help |
| 52 | This configuration indicates whether PSP Verstage needs to map the entire SPI ROM. |
| 53 | This is required only in Cezanne SoC at the moment. |