Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef _CPU_INTEL_MODEL_2065X_H |
| 18 | #define _CPU_INTEL_MODEL_2065X_H |
| 19 | |
Vladimir Serbinenko | 71f35eb | 2013-11-12 23:32:52 +0100 | [diff] [blame] | 20 | /* Nehalem bus clock is fixed at 133MHz */ |
| 21 | #define NEHALEM_BCLK 133 |
Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 22 | |
Arthur Heymans | b66ee55 | 2018-05-15 16:35:45 +0200 | [diff] [blame^] | 23 | #define CORE_THREAD_COUNT_MSR 0x35 |
Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 24 | #define MSR_FEATURE_CONFIG 0x13c |
| 25 | #define MSR_FLEX_RATIO 0x194 |
| 26 | #define FLEX_RATIO_LOCK (1 << 20) |
| 27 | #define FLEX_RATIO_EN (1 << 16) |
Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 28 | #define MSR_TEMPERATURE_TARGET 0x1a2 |
Alexander Couzens | ed48dfd | 2015-02-24 03:07:02 +0100 | [diff] [blame] | 29 | #define IA32_FERR_CAPABILITY 0x1f1 |
| 30 | #define FERR_ENABLE (1 << 0) |
Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 31 | |
| 32 | #define MSR_PIC_MSG_CONTROL 0x2e |
| 33 | #define MSR_PLATFORM_INFO 0xce |
| 34 | #define PLATFORM_INFO_SET_TDP (1 << 29) |
| 35 | |
| 36 | #define MSR_MISC_PWR_MGMT 0x1aa |
| 37 | #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) |
| 38 | #define MSR_TURBO_RATIO_LIMIT 0x1ad |
| 39 | #define MSR_POWER_CTL 0x1fc |
| 40 | |
| 41 | #define MSR_PKGC3_IRTL 0x60a |
| 42 | #define MSR_PKGC6_IRTL 0x60b |
| 43 | #define MSR_PKGC7_IRTL 0x60c |
| 44 | #define IRTL_VALID (1 << 15) |
| 45 | #define IRTL_1_NS (0 << 10) |
| 46 | #define IRTL_32_NS (1 << 10) |
| 47 | #define IRTL_1024_NS (2 << 10) |
| 48 | #define IRTL_32768_NS (3 << 10) |
| 49 | #define IRTL_1048576_NS (4 << 10) |
| 50 | #define IRTL_33554432_NS (5 << 10) |
| 51 | #define IRTL_RESPONSE_MASK (0x3ff) |
| 52 | |
| 53 | /* long duration in low dword, short duration in high dword */ |
| 54 | #define MSR_PKG_POWER_LIMIT 0x610 |
| 55 | #define PKG_POWER_LIMIT_MASK 0x7fff |
| 56 | #define PKG_POWER_LIMIT_EN (1 << 15) |
| 57 | #define PKG_POWER_LIMIT_CLAMP (1 << 16) |
| 58 | #define PKG_POWER_LIMIT_TIME_SHIFT 17 |
| 59 | #define PKG_POWER_LIMIT_TIME_MASK 0x7f |
| 60 | |
Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 61 | #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 |
| 62 | #define MSR_CONFIG_TDP_NOMINAL 0x648 |
| 63 | #define MSR_CONFIG_TDP_LEVEL1 0x649 |
| 64 | #define MSR_CONFIG_TDP_LEVEL2 0x64a |
| 65 | #define MSR_CONFIG_TDP_CONTROL 0x64b |
| 66 | #define MSR_TURBO_ACTIVATION_RATIO 0x64c |
| 67 | |
| 68 | /* P-state configuration */ |
| 69 | #define PSS_MAX_ENTRIES 16 |
| 70 | #define PSS_RATIO_STEP 1 |
| 71 | #define PSS_LATENCY_TRANSITION 10 |
| 72 | #define PSS_LATENCY_BUSMASTER 10 |
| 73 | |
| 74 | #ifdef __SMM__ |
| 75 | /* Lock MSRs */ |
| 76 | void intel_model_2065x_finalize_smm(void); |
| 77 | #else |
| 78 | /* Configure power limits for turbo mode */ |
| 79 | void set_power_limits(u8 power_limit_1_time); |
| 80 | int cpu_config_tdp_levels(void); |
Vladimir Serbinenko | 22dcdd9 | 2013-06-06 22:10:45 +0200 | [diff] [blame] | 81 | #endif |
| 82 | |
| 83 | #endif |