Felix Held | 6abaccf | 2022-01-10 20:55:01 +0100 | [diff] [blame] | 1 | /** @file |
| 2 | * |
| 3 | * This file is _NOT_ automatically generated in coreboot! |
| 4 | * |
| 5 | */ |
| 6 | |
| 7 | #ifndef __FSPMUPD_H__ |
| 8 | #define __FSPMUPD_H__ |
| 9 | |
| 10 | #include <FspUpd.h> |
| 11 | #include <FspUsb.h> |
| 12 | |
| 13 | #define FSPM_UPD_DXIO_DESCRIPTOR_COUNT 14 |
| 14 | #define FSPM_UPD_DDI_DESCRIPTOR_COUNT 5 |
| 15 | |
| 16 | /** Fsp M Configuration |
| 17 | **/ |
| 18 | typedef struct __packed { |
| 19 | /** Offset 0x0040**/ uint32_t bert_size; |
| 20 | /** Offset 0x0044**/ uint32_t tseg_size; |
| 21 | /** Offset 0x0048**/ uint32_t pci_express_base_addr; |
| 22 | /** Offset 0x004C**/ uint8_t misc_reserved[32]; |
| 23 | /** Offset 0x006C**/ uint32_t serial_port_base; |
| 24 | /** Offset 0x0070**/ uint32_t serial_port_use_mmio; |
| 25 | /** Offset 0x0074**/ uint32_t serial_port_baudrate; |
| 26 | /** Offset 0x0078**/ uint32_t serial_port_refclk; |
| 27 | /** Offset 0x007C**/ uint32_t serial_reserved; |
| 28 | /** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52]; |
| 29 | /** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets; |
| 30 | /** Offset 0x0359**/ uint8_t pcie_reserved[51]; |
| 31 | /** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT]; |
| 32 | /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; |
| 33 | /** Offset 0x03A6**/ uint8_t ccx_down_core_mode; |
| 34 | /** Offset 0x03A7**/ uint8_t ccx_disable_smt; |
| 35 | /** Offset 0x03A8**/ uint8_t ccx_reserved[32]; |
| 36 | /** Offset 0x03C8**/ uint8_t stt_control; |
| 37 | /** Offset 0x03C9**/ uint8_t stt_pcb_sensor_count; |
| 38 | /** Offset 0x03CA**/ uint16_t stt_min_limit; |
| 39 | /** Offset 0x03CC**/ uint16_t stt_m1; |
| 40 | /** Offset 0x03CE**/ uint16_t stt_m2; |
| 41 | /** Offset 0x03D0**/ uint16_t stt_m3; |
| 42 | /** Offset 0x03D2**/ uint16_t stt_m4; |
| 43 | /** Offset 0x03D4**/ uint16_t stt_m5; |
| 44 | /** Offset 0x03D6**/ uint16_t stt_m6; |
| 45 | /** Offset 0x03D8**/ uint16_t stt_c_apu; |
| 46 | /** Offset 0x03DA**/ uint16_t stt_c_gpu; |
| 47 | /** Offset 0x03DC**/ uint16_t stt_c_hs2; |
| 48 | /** Offset 0x03DE**/ uint16_t stt_alpha_apu; |
| 49 | /** Offset 0x03E0**/ uint16_t stt_alpha_gpu; |
| 50 | /** Offset 0x03E2**/ uint16_t stt_alpha_hs2; |
| 51 | /** Offset 0x03E4**/ uint16_t stt_skin_temp_apu; |
| 52 | /** Offset 0x03E6**/ uint16_t stt_skin_temp_gpu; |
| 53 | /** Offset 0x03E8**/ uint16_t stt_skin_temp_hs2; |
| 54 | /** Offset 0x03EA**/ uint16_t stt_error_coeff; |
| 55 | /** Offset 0x03EC**/ uint16_t stt_error_rate_coefficient; |
| 56 | /** Offset 0x03EE**/ uint8_t smartshift_enable; |
| 57 | /** Offset 0x03EF**/ uint32_t apu_only_sppt_limit; |
| 58 | /** Offset 0x03F3**/ uint32_t sustained_power_limit; |
| 59 | /** Offset 0x03F7**/ uint32_t fast_ppt_limit; |
| 60 | /** Offset 0x03FB**/ uint32_t slow_ppt_limit; |
| 61 | /** Offset 0x03FF**/ uint8_t system_configuration; |
| 62 | /** Offset 0x0400**/ uint8_t cppc_ctrl; |
| 63 | /** Offset 0x0401**/ uint8_t cppc_perf_limit_max_range; |
| 64 | /** Offset 0x0402**/ uint8_t cppc_perf_limit_min_range; |
| 65 | /** Offset 0x0403**/ uint8_t cppc_epp_max_range; |
| 66 | /** Offset 0x0404**/ uint8_t cppc_epp_min_range; |
| 67 | /** Offset 0x0405**/ uint8_t cppc_preferred_cores; |
| 68 | /** Offset 0x0406**/ uint8_t stapm_boost; |
| 69 | /** Offset 0x0407**/ uint32_t stapm_time_constant; |
| 70 | /** Offset 0x040B**/ uint32_t slow_ppt_time_constant; |
| 71 | /** Offset 0x040F**/ uint32_t thermctl_limit; |
| 72 | /** Offset 0x0413**/ uint8_t smu_soc_tuning_reserved[9]; |
| 73 | /** Offset 0x041C**/ uint8_t iommu_support; |
| 74 | /** Offset 0x041D**/ uint8_t pspp_policy; |
| 75 | /** Offset 0x041E**/ uint8_t enable_nb_azalia; |
| 76 | /** Offset 0x041F**/ uint8_t audio_io_ctl; |
| 77 | /** Offset 0x0420**/ uint8_t pdm_mic_selection; |
| 78 | /** Offset 0x0421**/ uint8_t hda_enable; |
| 79 | /** Offset 0x0422**/ uint8_t nbio_reserved[31]; |
| 80 | /** Offset 0x0441**/ uint32_t emmc0_mode; |
| 81 | /** Offset 0x0445**/ uint16_t emmc0_init_khz_preset; |
| 82 | /** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength; |
| 83 | /** Offset 0x0448**/ uint8_t emmc0_ddr50_driver_strength; |
| 84 | /** Offset 0x0449**/ uint8_t emmc0_sdr50_driver_strength; |
| 85 | /** Offset 0x044A**/ uint8_t UnusedUpdSpace0[85]; |
| 86 | /** Offset 0x049F**/ uint32_t gnb_ioapic_base; |
| 87 | /** Offset 0x04A3**/ uint8_t gnb_ioapic_id; |
| 88 | /** Offset 0x04A4**/ uint8_t fch_ioapic_id; |
| 89 | /** Offset 0x04A5**/ uint8_t sata_enable; |
| 90 | /** Offset 0x04A6**/ uint8_t fch_reserved[32]; |
| 91 | /** Offset 0x04C6**/ uint8_t s0i3_enable; |
| 92 | /** Offset 0x04C7**/ uint32_t telemetry_vddcrvddfull_scale_current; |
| 93 | /** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset; |
| 94 | /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; |
| 95 | /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; |
| 96 | /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; |
Felix Held | 7969a5c | 2022-11-29 17:54:18 +0100 | [diff] [blame] | 97 | /* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */ |
| 98 | /** Offset 0x04D8**/ uint32_t usb_phy_ptr; |
Chris.Wang | ad12b4f | 2022-12-28 17:07:48 +0800 | [diff] [blame] | 99 | /** Offset 0x04DC**/ uint8_t dxio_tx_vboost_enable; |
Patrick Huang | b643660 | 2023-03-21 16:35:11 +0800 | [diff] [blame^] | 100 | /** Offset 0x04DD**/ uint32_t vrm_current_limit_mA; |
| 101 | /** Offset 0x04E1**/ uint32_t vrm_maximum_current_limit_mA; |
| 102 | /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; |
| 103 | /** Offset 0x04E9**/ uint8_t UnusedUpdSpace2[279]; |
Felix Held | 6abaccf | 2022-01-10 20:55:01 +0100 | [diff] [blame] | 104 | /** Offset 0x0600**/ uint16_t UpdTerminator; |
| 105 | } FSP_M_CONFIG; |
| 106 | |
| 107 | /** Fsp M UPD Configuration |
| 108 | **/ |
| 109 | typedef struct __packed { |
| 110 | /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; |
| 111 | /** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd; |
| 112 | /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; |
| 113 | } FSPM_UPD; |
| 114 | |
Julian Schroeder | d2e278d | 2022-01-20 15:09:52 -0600 | [diff] [blame] | 115 | #define IMAGE_REVISION_MAJOR_VERSION 0x01 |
| 116 | #define IMAGE_REVISION_MINOR_VERSION 0x00 |
| 117 | #define IMAGE_REVISION_REVISION 0x05 |
| 118 | #define IMAGE_REVISION_BUILD_NUMBER 0x00 |
| 119 | |
Felix Held | 6abaccf | 2022-01-10 20:55:01 +0100 | [diff] [blame] | 120 | #endif |