blob: a859cd19afc577bdd21c0554aace9abb91b35cf9 [file] [log] [blame]
Angel Pons08d9f952020-04-03 01:22:39 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Max Blau517eda52019-04-29 23:48:31 +02002
3#include <device/pci_ops.h>
4#include <northbridge/intel/sandybridge/raminit_native.h>
5#include <southbridge/intel/common/pmbase.h>
Max Blau517eda52019-04-29 23:48:31 +02006#include <southbridge/intel/bd82x6x/pch.h>
7
Arthur Heymans2b28a162019-11-12 17:21:08 +01008void mainboard_pch_lpc_setup(void)
Max Blau517eda52019-04-29 23:48:31 +02009{
Max Blau517eda52019-04-29 23:48:31 +020010 u16 reg16;
11 reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4);
12 reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD)
13 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16);
14}
15
Max Blau517eda52019-04-29 23:48:31 +020016const struct southbridge_usb_port mainboard_usb_ports[] = {
17 {1, 0, 0},
18 {1, 0, 0},
19 {1, 0, 1},
20 {1, 0, 1},
21 {1, 0, 2},
22 {1, 0, 2},
23 {1, 0, 3},
24 {1, 0, 3},
25 {1, 0, 4},
26 {1, 0, 4},
27 {1, 0, 6},
28 {1, 0, 5},
29 {1, 0, 5},
30 {1, 0, 6},
31};
32
Max Blau517eda52019-04-29 23:48:31 +020033void mainboard_get_spd(spd_raw_data *spd, bool id_only)
34{
35 read_spd(&spd[0], 0x50, id_only);
36 read_spd(&spd[2], 0x52, id_only);
37}