blob: ca160945f2f52b50d4691c297e88e5d7bd629d83 [file] [log] [blame]
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +01001chip northbridge/intel/sandybridge
Nico Huberb0b25c82020-03-21 20:35:12 +01002 register "gfx" = "GMA_STATIC_DISPLAYS(0)"
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +01003 register "gpu_cpu_backlight" = "0x00000000"
4 register "gpu_dp_b_hotplug" = "0"
5 register "gpu_dp_c_hotplug" = "0"
6 register "gpu_dp_d_hotplug" = "0"
Angel Ponsdc0c0812020-09-02 19:17:30 +02007 register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +01008 register "gpu_panel_power_backlight_off_delay" = "0"
9 register "gpu_panel_power_backlight_on_delay" = "0"
10 register "gpu_panel_power_cycle_delay" = "0"
11 register "gpu_panel_power_down_delay" = "0"
12 register "gpu_panel_power_up_delay" = "0"
13 register "gpu_pch_backlight" = "0x00000000"
14
Peter Lemenkov7e128572019-11-27 22:39:52 +010015 device domain 0 on
16 subsystemid 0x17aa 0x21dd inherit
17
Arthur Heymansb5df65a2022-11-12 14:51:49 +010018 device ref host_bridge on end # Host bridge
19 device ref peg10 on end # PCIe Bridge for discrete graphics
20 device ref igd on end # Internal graphics VGA controller
Peter Lemenkov7e128572019-11-27 22:39:52 +010021
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010022 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010023 register "docking_supported" = "1"
24 register "gen1_dec" = "0x007c1611"
25 register "gen2_dec" = "0x00040069"
26 register "gen3_dec" = "0x000c0701"
27 register "gen4_dec" = "0x00000000"
28 register "gpi13_routing" = "2"
29 register "gpi6_routing" = "2"
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010030 register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
Angel Ponsaf4bd562021-12-28 13:05:56 +010031 register "pcie_port_coalesce" = "true"
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010032 register "sata_interface_speed_support" = "0x3"
33 register "sata_port_map" = "0x3b"
Patrick Rudolphc670a412017-04-28 17:28:32 +020034
35 register "spi_uvscc" = "0"
36 register "spi_lvscc" = "0x2005"
37
Arthur Heymansb5df65a2022-11-12 14:51:49 +010038 device ref mei1 on end # Management Engine Interface 1
39 device ref mei2 off end # Management Engine Interface 2
40 device ref me_ide_r off end # Management Engine IDE-R
41 device ref me_kt off end # Management Engine KT
42 device ref gbe off end # Intel Gigabit Ethernet
43 device ref ehci2 on end # USB2 EHCI #2
44 device ref hda on end # High Definition Audio Audio controller
45 device ref pcie_rp1 on end # PCIe Port #1
46 device ref pcie_rp2 on end # PCIe Port #2
47 device ref pcie_rp3 on end # PCIe Port #3
48 device ref pcie_rp4 on end # PCIe Port #4
49 device ref pcie_rp5 on end # PCIe Port #5
50 device ref pcie_rp6 on end # PCIe Port #6
51 device ref pcie_rp7 off end # PCIe Port #7
52 device ref pcie_rp8 off end # PCIe Port #8
53 device ref ehci1 on end # USB2 EHCI #1
54 device ref pci_bridge off end # PCI bridge
55 device ref lpc on # LPC bridge PCI-LPC bridge
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010056 chip ec/lenovo/pmh7
57 register "backlight_enable" = "0x01"
58 register "dock_event_enable" = "0x01"
Peter Lemenkov7e128572019-11-27 22:39:52 +010059 device pnp ff.1 on end # dummy
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010060 end
61 chip ec/lenovo/h8
Patrick Rudolphc670a412017-04-28 17:28:32 +020062 register "config0" = "0xa7"
63 register "config1" = "0x09"
64 register "config2" = "0xa0"
65 register "config3" = "0xc2"
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010066
Patrick Rudolphc670a412017-04-28 17:28:32 +020067 register "beepmask0" = "0x00"
68 register "beepmask1" = "0x86"
69 register "has_power_management_beeps" = "0"
70 register "event2_enable" = "0xff"
71 register "event3_enable" = "0xff"
72 register "event4_enable" = "0xff"
73 register "event5_enable" = "0xff"
74 register "event6_enable" = "0xff"
75 register "event7_enable" = "0xff"
76 register "event8_enable" = "0xff"
77 register "event9_enable" = "0xff"
78 register "eventa_enable" = "0xff"
79 register "eventb_enable" = "0xff"
80 register "eventc_enable" = "0xff"
81 register "eventd_enable" = "0xff"
82 register "evente_enable" = "0xff"
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010083
84 device pnp ff.2 on # dummy
85 io 0x60 = 0x62
86 io 0x62 = 0x66
87 io 0x64 = 0x1600
88 io 0x66 = 0x1604
89 end
90 end
Peter Lemenkov7e128572019-11-27 22:39:52 +010091 end # LPC bridge
Arthur Heymansb5df65a2022-11-12 14:51:49 +010092 device ref sata1 on end # SATA Controller 1
93 device ref smbus on # SMBus
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +010094 chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
Peter Lemenkov7e128572019-11-27 22:39:52 +010095 device i2c 54 on end
96 device i2c 55 on end
97 device i2c 56 on end
98 device i2c 57 on end
99 device i2c 5c on end
100 device i2c 5d on end
101 device i2c 5e on end
102 device i2c 5f on end
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +0100103 end
Peter Lemenkov7e128572019-11-27 22:39:52 +0100104 end # SMBus
Arthur Heymansb5df65a2022-11-12 14:51:49 +0100105 device ref sata2 off end # SATA Controller 2
106 device ref thermal off end # Thermal
Patrick Rudolphaae6e9c2016-12-30 17:02:04 +0100107 end
108 end
109end