Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 1 | #include <console/console.h> |
| 2 | #include <arch/smp/mpspec.h> |
| 3 | #include <device/pci.h> |
| 4 | #include <string.h> |
| 5 | #include <stdint.h> |
| 6 | |
| 7 | void *smp_write_config_table(void *v, unsigned long * processor_map) |
| 8 | { |
| 9 | static const char sig[4] = "PCMP"; |
| 10 | static const char oem[8] = "TYAN "; |
| 11 | static const char productid[12] = "S2882 "; |
| 12 | struct mp_config_table *mc; |
| 13 | |
| 14 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 15 | memset(mc, 0, sizeof(*mc)); |
| 16 | |
| 17 | memcpy(mc->mpc_signature, sig, sizeof(sig)); |
| 18 | mc->mpc_length = sizeof(*mc); /* initially just the header */ |
| 19 | mc->mpc_spec = 0x04; |
| 20 | mc->mpc_checksum = 0; /* not yet computed */ |
| 21 | memcpy(mc->mpc_oem, oem, sizeof(oem)); |
| 22 | memcpy(mc->mpc_productid, productid, sizeof(productid)); |
| 23 | mc->mpc_oemptr = 0; |
| 24 | mc->mpc_oemsize = 0; |
| 25 | mc->mpc_entry_count = 0; /* No entries yet... */ |
| 26 | mc->mpc_lapic = LAPIC_ADDR; |
| 27 | mc->mpe_length = 0; |
| 28 | mc->mpe_checksum = 0; |
| 29 | mc->reserved = 0; |
| 30 | |
| 31 | smp_write_processors(mc, processor_map); |
| 32 | |
| 33 | |
| 34 | /*Bus: Bus ID Type*/ |
| 35 | smp_write_bus(mc, 0, "PCI "); |
| 36 | smp_write_bus(mc, 1, "PCI "); |
| 37 | smp_write_bus(mc, 2, "PCI "); |
| 38 | smp_write_bus(mc, 3, "PCI "); |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 39 | smp_write_bus(mc, 4, "PCI "); |
| 40 | smp_write_bus(mc, 5, "ISA "); |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 41 | /*I/O APICs: APIC ID Version State Address*/ |
| 42 | smp_write_ioapic(mc, 2, 0x11, 0xfec00000); |
| 43 | { |
| 44 | struct pci_dev *dev; |
| 45 | uint32_t base; |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 46 | dev = dev_find_slot(1, PCI_DEVFN(0x1,1)); |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 47 | if (dev) { |
| 48 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 49 | base &= PCI_BASE_ADDRESS_MEM_MASK; |
| 50 | smp_write_ioapic(mc, 3, 0x11, base); |
| 51 | } |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 52 | dev = dev_find_slot(1, PCI_DEVFN(0x2,1)); |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 53 | if (dev) { |
| 54 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 55 | base &= PCI_BASE_ADDRESS_MEM_MASK; |
| 56 | smp_write_ioapic(mc, 4, 0x11, base); |
| 57 | } |
| 58 | } |
| 59 | |
| 60 | /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 61 | */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x0); |
| 62 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x2, 0x1); |
| 63 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x2); |
| 64 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x3, 0x2, 0x3); |
| 65 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x4, 0x2, 0x4); |
| 66 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x6, 0x2, 0x6); |
| 67 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x7, 0x2, 0x7); |
| 68 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8); |
| 69 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xc, 0x2, 0xc); |
| 70 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xd, 0x2, 0xd); |
| 71 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xe, 0x2, 0xe); |
| 72 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xf, 0x2, 0xf); |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 73 | |
| 74 | //??? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x1f, 0x2, 0x13); |
| 75 | |
| 76 | |
| 77 | //On Board AMD USB |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 78 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x3, 0x2, 0x13); |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 79 | |
| 80 | //On Board ATI Display Adapter |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 81 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x18, 0x2, 0x12); |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 82 | #if 0 |
| 83 | //Slot 5 PCI 32 |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 84 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, 0x2, 0x10); |
| 85 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x11, 0x2, 0x11); |
| 86 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x12, 0x2, 0x12); // |
| 87 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x13, 0x2, 0x13); // |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 88 | #endif |
| 89 | //Onboard SI Serial ATA |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 90 | // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, 0x2, 0x11); |
Ronald G. Minnich | b56ef07 | 2003-10-15 20:05:11 +0000 | [diff] [blame^] | 91 | #if 1 |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 92 | //Slot 3 PCIX 100/66 |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 93 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x3, 0x3); |
| 94 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x21, 0x3, 0x0); |
| 95 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x22, 0x3, 0x1);// |
| 96 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x23, 0x3, 0x2);// |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 97 | |
| 98 | //Slot 4 PCIX 100/66 |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 99 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1c, 0x3, 0x2); |
| 100 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1d, 0x3, 0x3);// |
| 101 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1e, 0x3, 0x0);// |
| 102 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1f, 0x3, 0x1);// |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 103 | #endif |
| 104 | //Onboard adaptec scsi |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 105 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x3, 0x0); |
| 106 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x3, 0x1); |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 107 | //On Board NIC |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 108 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x24, 0x3, 0x0); |
| 109 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x25, 0x3, 0x1); |
Ronald G. Minnich | b56ef07 | 2003-10-15 20:05:11 +0000 | [diff] [blame^] | 110 | #if 1 |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 111 | //Slot 1 PCI-X 133/100/66 |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 112 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xc, 0x4, 0x0); |
| 113 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xd, 0x4, 0x1); |
| 114 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xe, 0x4, 0x2); // |
| 115 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xf, 0x4, 0x3); // |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 116 | |
| 117 | //Slot 2 PCI-X 133/100/66 |
Ronald G. Minnich | 3ff7bda | 2003-09-25 22:04:19 +0000 | [diff] [blame] | 118 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x4, 0x1); |
| 119 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x19, 0x4, 0x2); |
| 120 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1a, 0x4, 0x3);// |
| 121 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1b, 0x4, 0x0);// |
Ronald G. Minnich | fa2df75 | 2003-08-27 14:33:13 +0000 | [diff] [blame] | 122 | #endif |
| 123 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ |
| 124 | smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0); |
| 125 | smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); |
| 126 | /* There is no extension information... */ |
| 127 | |
| 128 | /* Compute the checksums */ |
| 129 | mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 130 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 131 | printk_debug("Wrote the mp table end at: %p - %p\n", |
| 132 | mc, smp_next_mpe_entry(mc)); |
| 133 | return smp_next_mpe_entry(mc); |
| 134 | } |
| 135 | |
| 136 | unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) |
| 137 | { |
| 138 | void *v; |
| 139 | v = smp_write_floating_table(addr); |
| 140 | return (unsigned long)smp_write_config_table(v, processor_map); |
| 141 | } |