Vinod Polimera | 3b4c45e | 2020-03-03 12:13:26 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/mmio.h> |
| 4 | #include <console/console.h> |
| 5 | #include <delay.h> |
| 6 | #include <edid.h> |
| 7 | #include <soc/display/mdssreg.h> |
| 8 | |
Vinod Polimera | b524d2b | 2020-10-30 15:34:03 +0530 | [diff] [blame^] | 9 | #define MDSS_MDP_MAX_PREFILL_FETCH 24 |
Vinod Polimera | 3b4c45e | 2020-03-03 12:13:26 +0530 | [diff] [blame] | 10 | |
| 11 | static void mdss_source_pipe_config(struct edid *edid) |
| 12 | { |
| 13 | uint32_t img_size, out_size, stride; |
| 14 | uint32_t fb_off = 0; |
| 15 | uint32_t flip_bits = 0; |
| 16 | uint32_t src_xy = 0; |
| 17 | uint32_t dst_xy = 0; |
| 18 | |
| 19 | /* write active region size*/ |
| 20 | img_size = (edid->mode.va << 16) | edid->mode.ha; |
| 21 | out_size = img_size; |
| 22 | stride = (edid->mode.ha * edid->framebuffer_bits_per_pixel/8); |
| 23 | |
| 24 | if (!fb_off) { /* left */ |
| 25 | dst_xy = (edid->mode.vborder << 16) | edid->mode.hborder; |
| 26 | src_xy = dst_xy; |
| 27 | } else { /* right */ |
| 28 | dst_xy = (edid->mode.vborder << 16); |
| 29 | src_xy = (edid->mode.vborder << 16) | fb_off; |
| 30 | } |
| 31 | |
| 32 | printk(BIOS_INFO, "%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 33 | __func__, out_size, fb_off, src_xy, dst_xy); |
| 34 | |
| 35 | write32(&mdp_sspp->sspp_src_ystride0, stride); |
| 36 | write32(&mdp_sspp->sspp_src_size, out_size); |
| 37 | write32(&mdp_sspp->sspp_out_size, out_size); |
| 38 | write32(&mdp_sspp->sspp_src_xy, src_xy); |
| 39 | write32(&mdp_sspp->sspp_out_xy, dst_xy); |
| 40 | |
| 41 | /* Tight Packing 4bpp Alpha 8-bit A R B G */ |
| 42 | write32(&mdp_sspp->sspp_src_format, 0x000236ff); |
| 43 | write32(&mdp_sspp->sspp_src_unpack_pattern, 0x03020001); |
| 44 | |
| 45 | flip_bits |= BIT(31); |
| 46 | write32(&mdp_sspp->sspp_sw_pic_ext_c0_req_pixels, out_size); |
| 47 | write32(&mdp_sspp->sspp_sw_pic_ext_c1c2_req_pixels, out_size); |
| 48 | write32(&mdp_sspp->sspp_sw_pic_ext_c3_req_pixels, out_size); |
| 49 | write32(&mdp_sspp->sspp_src_op_mode, flip_bits); |
| 50 | } |
| 51 | |
| 52 | static void mdss_vbif_setup(void) |
| 53 | { |
| 54 | write32(&vbif_rt->vbif_out_axi_amemtype_conf0, 0x33333333); |
| 55 | write32(&vbif_rt->vbif_out_axi_amemtype_conf1, 0x00333333); |
| 56 | } |
| 57 | |
| 58 | static void mdss_intf_tg_setup(struct edid *edid) |
| 59 | { |
| 60 | uint32_t hsync_period, vsync_period; |
| 61 | uint32_t hsync_start_x, hsync_end_x; |
| 62 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
| 63 | |
| 64 | hsync_period = edid->mode.ha + edid->mode.hbl; |
| 65 | vsync_period = edid->mode.va + edid->mode.vbl; |
| 66 | hsync_start_x = edid->mode.hbl - edid->mode.hso; |
| 67 | hsync_end_x = hsync_period - edid->mode.hso - 1; |
| 68 | display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period; |
| 69 | display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1; |
| 70 | hsync_ctl = (hsync_period << 16) | edid->mode.hspw; |
| 71 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 72 | |
| 73 | write32(&mdp_intf->intf_hsync_ctl, hsync_ctl); |
| 74 | write32(&mdp_intf->intf_vysnc_period_f0, |
| 75 | vsync_period * hsync_period); |
| 76 | write32(&mdp_intf->intf_vysnc_pulse_width_f0, |
| 77 | edid->mode.vspw * hsync_period); |
| 78 | write32(&mdp_intf->intf_disp_hctl, display_hctl); |
| 79 | write32(&mdp_intf->intf_disp_v_start_f0, display_vstart); |
| 80 | write32(&mdp_intf->intf_disp_v_end_f0, display_vend); |
| 81 | write32(&mdp_intf->intf_underflow_color, 0x00); |
| 82 | write32(&mdp_intf->intf_panel_format, 0x2100); |
| 83 | } |
| 84 | |
| 85 | static void mdss_intf_fetch_start_config(struct edid *edid) |
| 86 | { |
| 87 | uint32_t v_total, h_total, fetch_start, vfp_start; |
| 88 | uint32_t prefetch_avail, prefetch_needed; |
| 89 | uint32_t fetch_enable = BIT(31); |
| 90 | |
| 91 | /* |
| 92 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 93 | * Programmable fetch is not needed if vertical back porch |
Vinod Polimera | b524d2b | 2020-10-30 15:34:03 +0530 | [diff] [blame^] | 94 | * plus vertical pulse width plus extra line for the extra h_total |
| 95 | * added during fetch start is >= 24. |
Vinod Polimera | 3b4c45e | 2020-03-03 12:13:26 +0530 | [diff] [blame] | 96 | */ |
Vinod Polimera | b524d2b | 2020-10-30 15:34:03 +0530 | [diff] [blame^] | 97 | if ((edid->mode.vbl - edid->mode.vso + 1) >= MDSS_MDP_MAX_PREFILL_FETCH) |
Vinod Polimera | 3b4c45e | 2020-03-03 12:13:26 +0530 | [diff] [blame] | 98 | return; |
| 99 | |
| 100 | /* |
| 101 | * Fetch should always be outside the active lines. If the fetching |
| 102 | * is programmed within active region, hardware behavior is unknown. |
| 103 | */ |
| 104 | v_total = edid->mode.va + edid->mode.vbl; |
| 105 | h_total = edid->mode.ha + edid->mode.hbl; |
| 106 | vfp_start = edid->mode.va + edid->mode.vbl - edid->mode.vso; |
| 107 | prefetch_avail = v_total - vfp_start; |
| 108 | prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - edid->mode.vbl + edid->mode.vso; |
| 109 | |
| 110 | /* |
| 111 | * In some cases, vertical front porch is too high. In such cases limit |
| 112 | * the mdp fetch lines as the last (25 - vbp - vpw) lines of |
| 113 | * vertical front porch. |
| 114 | */ |
| 115 | if (prefetch_avail > prefetch_needed) |
| 116 | prefetch_avail = prefetch_needed; |
| 117 | |
| 118 | fetch_start = (v_total - prefetch_avail) * h_total + h_total + 1; |
| 119 | write32(&mdp_intf->intf_prof_fetch_start, fetch_start); |
| 120 | write32(&mdp_intf->intf_config, fetch_enable); |
| 121 | } |
| 122 | |
| 123 | static void mdss_layer_mixer_setup(struct edid *edid) |
| 124 | { |
| 125 | uint32_t mdp_rgb_size; |
| 126 | uint32_t left_staging_level; |
| 127 | |
| 128 | /* write active region size*/ |
| 129 | mdp_rgb_size = (edid->mode.va << 16) | edid->mode.ha; |
| 130 | |
| 131 | write32(&mdp_layer_mixer->layer_out_size, mdp_rgb_size); |
| 132 | write32(&mdp_layer_mixer->layer_op_mode, 0x0); |
| 133 | for (int i = 0; i < 6; i++) { |
| 134 | write32(&mdp_layer_mixer->layer_blend[i].layer_blend_op, 0x100); |
| 135 | write32(&mdp_layer_mixer->layer_blend[i].layer_blend_const_alpha, 0x00ff0000); |
| 136 | } |
| 137 | |
| 138 | /* Enable border fill */ |
| 139 | left_staging_level = BIT(24); |
| 140 | left_staging_level |= BIT(1); |
| 141 | |
| 142 | /* Base layer for layer mixer 0 */ |
| 143 | write32(&mdp_ctl->ctl_layer0, left_staging_level); |
| 144 | } |
| 145 | |
| 146 | static void mdss_vbif_qos_remapper_setup(void) |
| 147 | { |
| 148 | /* |
| 149 | * VBIF remapper registers are used for translating internal display hardware |
| 150 | * priority level (from 0 to 7) into system fabric priority level. |
| 151 | * These remapper settings are defined for all the clients which corresponds |
| 152 | * to the xin clients connected to SSPP on VBIF. |
| 153 | */ |
| 154 | write32(&vbif_rt->qos_rp_remap[0].vbif_xinl_qos_rp_remap, 0x00000003); |
| 155 | write32(&vbif_rt->qos_rp_remap[1].vbif_xinl_qos_rp_remap, 0x11111113); |
| 156 | write32(&vbif_rt->qos_rp_remap[2].vbif_xinl_qos_rp_remap, 0x22222224); |
| 157 | write32(&vbif_rt->qos_rp_remap[3].vbif_xinl_qos_rp_remap, 0x33333334); |
| 158 | write32(&vbif_rt->qos_rp_remap[4].vbif_xinl_qos_rp_remap, 0x44444445); |
| 159 | write32(&vbif_rt->qos_rp_remap[7].vbif_xinl_qos_rp_remap, 0x77777776); |
| 160 | write32(&vbif_rt->qos_lvl_remap[0].vbif_xinl_qos_lvl_remap, 0x00000003); |
| 161 | write32(&vbif_rt->qos_lvl_remap[1].vbif_xinl_qos_lvl_remap, 0x11111113); |
| 162 | write32(&vbif_rt->qos_lvl_remap[2].vbif_xinl_qos_lvl_remap, 0x22222224); |
| 163 | write32(&vbif_rt->qos_lvl_remap[3].vbif_xinl_qos_lvl_remap, 0x33333334); |
| 164 | write32(&vbif_rt->qos_lvl_remap[4].vbif_xinl_qos_lvl_remap, 0x44444445); |
| 165 | write32(&vbif_rt->qos_lvl_remap[5].vbif_xinl_qos_lvl_remap, 0x77777776); |
| 166 | } |
| 167 | |
| 168 | void mdp_dsi_video_config(struct edid *edid) |
| 169 | { |
| 170 | mdss_intf_tg_setup(edid); |
| 171 | mdss_intf_fetch_start_config(edid); |
| 172 | mdss_vbif_setup(); |
| 173 | mdss_vbif_qos_remapper_setup(); |
| 174 | mdss_source_pipe_config(edid); |
| 175 | mdss_layer_mixer_setup(edid); |
| 176 | |
| 177 | /* Select Video Mode Interface */ |
| 178 | write32(&mdp_ctl->ctl_top, 0x0); |
| 179 | |
| 180 | /* PPB0 to INTF1 */ |
| 181 | write32(&mdp_ctl->ctl_intf_active, BIT(1)); |
| 182 | write32(&mdp_intf->intf_mux, 0x0F0000); |
| 183 | } |
| 184 | |
| 185 | void mdp_dsi_video_on(void) |
| 186 | { |
| 187 | uint32_t ctl0_reg_val; |
| 188 | |
| 189 | ctl0_reg_val = VIG_0 | LAYER_MIXER_0 | CTL | INTF; |
| 190 | write32(&mdp_ctl->ctl_intf_flush, 0x2); |
| 191 | write32(&mdp_ctl->ctl_flush, ctl0_reg_val); |
| 192 | } |