Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 4 | #include <assert.h> |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 5 | #include <console/console.h> |
Liangfeng Wu | 737a7cc | 2016-09-15 17:16:54 +0800 | [diff] [blame] | 6 | #include <soc/clock.h> |
| 7 | #include <soc/grf.h> |
| 8 | #include <soc/soc.h> |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 9 | #include <soc/usb.h> |
| 10 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 11 | /* SuperSpeed over Type-C is hard. We don't care about speed in firmware: just |
| 12 | * gate off the SuperSpeed lines to have an unimpaired USB 2.0 connection. */ |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 13 | static void isolate_tcphy(struct rk3399_tcphy *tcphy) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 14 | { |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 15 | write32(&tcphy->isolation_ctrl, |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 16 | TCPHY_ISOLATION_CTRL_EN | |
| 17 | TCPHY_ISOLATION_CTRL_CMN_EN | |
| 18 | TCPHY_ISOLATION_CTRL_MODE_SEL | |
| 19 | TCPHY_ISOLATION_CTRL_LN_EN(7) | |
| 20 | TCPHY_ISOLATION_CTRL_LN_EN(6) | |
| 21 | TCPHY_ISOLATION_CTRL_LN_EN(5) | |
| 22 | TCPHY_ISOLATION_CTRL_LN_EN(4) | |
| 23 | TCPHY_ISOLATION_CTRL_LN_EN(3) | |
| 24 | TCPHY_ISOLATION_CTRL_LN_EN(2) | |
| 25 | TCPHY_ISOLATION_CTRL_LN_EN(1) | |
| 26 | TCPHY_ISOLATION_CTRL_LN_EN(0)); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 27 | } |
| 28 | |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 29 | static void tcphy_cfg_24m(struct rk3399_tcphy *tcphy) |
| 30 | { |
| 31 | u32 i; |
| 32 | |
| 33 | /* cmn_ref_clk_sel = 3, select the 24Mhz for clk parent |
| 34 | * cmn_psm_clk_dig_div = 2, set the clk division to 2 */ |
| 35 | write32(&tcphy->pma_cmn_ctrl1, 2 << 10 | 3 << 4); |
| 36 | for (i = 0; i < 4; i++) { |
| 37 | /* The following PHY configuration assumes a |
| 38 | * 24 MHz reference clock */ |
| 39 | write32(&tcphy->lane[i].xcvr_diag_lane_fcm_en_mgn, 0x90); |
| 40 | write32(&tcphy->lane[i].tx_rcvdet_en_tmr, 0x960); |
| 41 | write32(&tcphy->lane[i].tx_rcvdet_st_tmr, 0x30); |
| 42 | } |
| 43 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 44 | clrsetbits32(&tcphy->cmn_diag_hsclk_sel, |
| 45 | TCPHY_CMN_HSCLK_PLL_MASK, TCPHY_CMN_HSCLK_PLL_CONFIG); |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 46 | } |
| 47 | |
| 48 | static void tcphy_phy_init(struct rk3399_tcphy *tcphy) |
| 49 | { |
| 50 | u32 i; |
| 51 | |
| 52 | tcphy_cfg_24m(tcphy); |
| 53 | |
| 54 | for (i = 0; i < 4; i++) { |
| 55 | /* Enable transmitter reset pull down override for all lanes*/ |
| 56 | write32(&tcphy->lane[i].tx_diag_tx_drv, 0x2000); |
| 57 | /* Disable transmitter low current mode, disable TX |
| 58 | * driver common mode, disable TX post-emphasis*/ |
| 59 | write32(&tcphy->lane[i].tx_psc_a2, 0x0000); |
| 60 | } |
| 61 | |
| 62 | isolate_tcphy(tcphy); |
| 63 | } |
| 64 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 65 | static void reset_dwc3(struct rockchip_usb_dwc3 *dwc3) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 66 | { |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 67 | /* Before Resetting PHY, put Core in Reset */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 68 | setbits32(&dwc3->ctl, DWC3_GCTL_CORESOFTRESET); |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 69 | /* Assert USB3 PHY reset */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 70 | setbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 71 | /* Assert USB2 PHY reset */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 72 | setbits32(&dwc3->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 73 | } |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 74 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 75 | static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) |
| 76 | { |
| 77 | u32 usb2phycfg = read32(&dwc3->usb2phycfg); |
| 78 | u32 ctl = read32(&dwc3->ctl); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 79 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 80 | /* Ensure reset_dwc3() has been called before this. */ |
| 81 | assert(ctl & DWC3_GCTL_CORESOFTRESET); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 82 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 83 | /* Clear USB3 PHY reset (oddly enough, this is really necessary). */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 84 | clrbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 85 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 86 | /* Clear USB2 PHY and core reset. */ |
| 87 | usb2phycfg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; |
| 88 | ctl &= ~DWC3_GCTL_CORESOFTRESET; |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 89 | |
| 90 | /* We are hard-coding DWC3 core to Host Mode */ |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 91 | ctl &= ~DWC3_GCTL_PRTCAP_MASK; |
| 92 | ctl |= DWC3_GCTL_PRTCAP_HOST; |
| 93 | |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 94 | /* |
| 95 | * Configure USB phy interface of DWC3 core. |
| 96 | * For Rockchip rk3399 SOC DWC3 core: |
| 97 | * 1. Clear U2_FREECLK_EXITS. |
| 98 | * 2. Select UTMI+ PHY with 16-bit interface. |
| 99 | * 3. Set USBTRDTIM to the corresponding value |
| 100 | * according to the UTMI+ PHY interface. |
| 101 | */ |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 102 | usb2phycfg &= ~(DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS | |
| 103 | DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | |
| 104 | DWC3_GUSB2PHYCFG_PHYIF_MASK); |
| 105 | usb2phycfg |= DWC3_GUSB2PHYCFG_PHYIF(1) | |
| 106 | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); |
| 107 | |
| 108 | write32(&dwc3->usb2phycfg, usb2phycfg); |
| 109 | write32(&dwc3->ctl, ctl); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 110 | } |
| 111 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 112 | void reset_usb_otg0(void) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 113 | { |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 114 | printk(BIOS_DEBUG, "Starting DWC3 and TCPHY reset for USB OTG0\n"); |
| 115 | |
Liangfeng Wu | 737a7cc | 2016-09-15 17:16:54 +0800 | [diff] [blame] | 116 | /* Keep whole USB OTG0 controller in reset, then |
| 117 | * configure controller to work in USB 2.0 only mode. */ |
| 118 | write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 5)); |
| 119 | write32(&rk3399_grf->usb3otg0_con1, RK_CLRSETBITS(0xf << 12, 1 << 0)); |
| 120 | write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 5)); |
| 121 | |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 122 | tcphy_phy_init(rockchip_usb_otg0_phy); |
| 123 | |
| 124 | /* Clear TCPHY0 reset */ |
| 125 | write32(&cru_ptr->softrst_con[9], RK_CLRBITS(1 << 5)); |
| 126 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 127 | reset_dwc3(rockchip_usb_otg0_dwc3); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 128 | } |
| 129 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 130 | void reset_usb_otg1(void) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 131 | { |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 132 | printk(BIOS_DEBUG, "Starting DWC3 and TCPHY reset for USB OTG1\n"); |
| 133 | |
Liangfeng Wu | 737a7cc | 2016-09-15 17:16:54 +0800 | [diff] [blame] | 134 | /* Keep whole USB OTG1 controller in reset, then |
| 135 | * configure controller to work in USB 2.0 only mode. */ |
| 136 | write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 6)); |
| 137 | write32(&rk3399_grf->usb3otg1_con1, RK_CLRSETBITS(0xf << 12, 1 << 0)); |
| 138 | write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 6)); |
| 139 | |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 140 | tcphy_phy_init(rockchip_usb_otg1_phy); |
| 141 | |
| 142 | /* Clear TCPHY1 reset */ |
| 143 | write32(&cru_ptr->softrst_con[9], RK_CLRBITS(1 << 13)); |
| 144 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 145 | reset_dwc3(rockchip_usb_otg1_dwc3); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 146 | } |
| 147 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 148 | void setup_usb_otg0(void) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 149 | { |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 150 | /* Clear pipe reset */ |
| 151 | write32(&cru_ptr->softrst_con[9], RK_CLRBITS(1 << 4)); |
| 152 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 153 | setup_dwc3(rockchip_usb_otg0_dwc3); |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 154 | printk(BIOS_DEBUG, "DWC3 and TCPHY setup for USB OTG0 finished\n"); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 155 | } |
| 156 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 157 | void setup_usb_otg1(void) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 158 | { |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 159 | /* Clear pipe reset */ |
| 160 | write32(&cru_ptr->softrst_con[9], RK_CLRBITS(1 << 12)); |
| 161 | |
Julius Werner | 785ff1b | 2016-08-03 19:18:39 -0700 | [diff] [blame] | 162 | setup_dwc3(rockchip_usb_otg1_dwc3); |
William wu | 801a8ef | 2016-10-01 20:58:21 +0800 | [diff] [blame] | 163 | printk(BIOS_DEBUG, "DWC3 and TCPHY setup for USB OTG1 finished\n"); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 164 | } |