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review.coreboot.org / coreboot / b438dab36757915608fdfb2a4ef7a87c323b43c1 / . / src / mainboard / google / hatch / variants / kaisa / gpio.c
blob: 60842a4e546b9a176ce5c0458d0aa1c35aa9d0e8 [file] [log] [blame]
Andrew McRaeb438dab2020-04-15 16:10:58 +1000[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
3
4#include <baseboard/gpio.h>
5#include <baseboard/variants.h>
6#include <commonlib/helpers.h>
7
8static const struct pad_config gpio_table[] = {
9 /* A16 : SD_OC_ODL */
10 PAD_CFG_GPI(GPP_A16, NONE, DEEP),
11 /* A18 : LAN_PE_ISOLATE_ODL */
12 PAD_CFG_GPO(GPP_A18, 1, DEEP),
13 /* A23 : M2_WLAN_INT_ODL */
14 PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
15
16 /* B5 : LAN_CLKREQ_ODL */
17 PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
18
19 /* C0 : SMBCLK */
20 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
21 /* C1 : SMBDATA */
22 PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
23 /* C6: M2_WLAN_WAKE_ODL */
24 PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
25 /* C7 : LAN_WAKE_ODL */
26 PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
27 /* C10 : PCH_PCON_RST_ODL */
28 PAD_CFG_GPO(GPP_C10, 1, DEEP),
29 /* C11 : PCH_PCON_PDB_ODL */
30 PAD_CFG_GPO(GPP_C11, 1, DEEP),
31 /* C15 : WLAN_OFF_L */
32 PAD_CFG_GPO(GPP_C15, 1, DEEP),
33
34 /* E2 : EN_PP_MST_OD */
35 PAD_CFG_GPO(GPP_E2, 1, DEEP),
36 /* E9 : USB_A0_OC_ODL */
37 PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
38 /* E10 : USB_A1_OC_ODL */
39 PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
40
41 /* F11 : EMMC_CMD */
42 PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
43 /* F12 : EMMC_DATA0 */
44 PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
45 /* F13 : EMMC_DATA1 */
46 PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
47 /* F14 : EMMC_DATA2 */
48 PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
49 /* F15 : EMMC_DATA3 */
50 PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
51 /* F16 : EMMC_DATA4 */
52 PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
53 /* F17 : EMMC_DATA5 */
54 PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
55 /* F18 : EMMC_DATA6 */
56 PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
57 /* F19 : EMMC_DATA7 */
58 PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
59 /* F20 : EMMC_RCLK */
60 PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
61 /* F21 : EMMC_CLK */
62 PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
63 /* F22 : EMMC_RST_L */
64 PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
65
66 /* H4: PCH_I2C_PCON_SDA */
67 PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
68 /* H5: PCH_I2C_PCON_SCL */
69 PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
70 /* H22 : PWM_PP3300_BIOZZER */
71 PAD_CFG_GPO(GPP_H22, 0, DEEP),
72};
73
74const struct pad_config *override_gpio_table(size_t *num)
75{
76 *num = ARRAY_SIZE(gpio_table);
77 return gpio_table;
78}
79
80/* Early pad configuration in bootblock */
81static const struct pad_config early_gpio_table[] = {
82 /* B14 : GPP_B14_STRAP */
83 PAD_NC(GPP_B14, NONE),
84 /* B22 : GPP_B22_STRAP */
85 PAD_NC(GPP_B22, NONE),
86 /* E19 : GPP_E19_STRAP */
87 PAD_NC(GPP_E19, NONE),
88 /* E21 : GPP_E21_STRAP */
89 PAD_NC(GPP_E21, NONE),
90 /* B15 : H1_SLAVE_SPI_CS_L */
91 PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
92 /* B16 : H1_SLAVE_SPI_CLK */
93 PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
94 /* B17 : H1_SLAVE_SPI_MISO_R */
95 PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
96 /* B18 : H1_SLAVE_SPI_MOSI_R */
97 PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
98 /* C14 : BT_DISABLE_L */
99 PAD_CFG_GPO(GPP_C14, 0, DEEP),
100 /* PCH_WP_OD */
101 PAD_CFG_GPI(GPP_C20, NONE, DEEP),
102 /* C21 : H1_PCH_INT_ODL */
103 PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
104 /* C23 : WLAN_PE_RST# */
105 PAD_CFG_GPO(GPP_C23, 1, DEEP),
106 /* E1 : M2_SSD_PEDET */
107 PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
108 /* E5 : SATA_DEVSLP1 */
109 PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
110};
111
112const struct pad_config *variant_early_gpio_table(size_t *num)
113{
114 *num = ARRAY_SIZE(early_gpio_table);
115 return early_gpio_table;
116}