Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Alder Lake Platform Stepping and IDs |
| 5 | * Document number: 619362, 619501 |
| 6 | * Chapter number: 2, 14 |
| 7 | */ |
| 8 | |
| 9 | #include <arch/cpu.h> |
| 10 | #include <device/pci_ops.h> |
| 11 | #include <console/console.h> |
| 12 | #include <cpu/intel/microcode.h> |
| 13 | #include <cpu/x86/msr.h> |
| 14 | #include <cpu/x86/name.h> |
| 15 | #include <device/pci.h> |
| 16 | #include <device/pci_ids.h> |
| 17 | #include <intelblocks/mp_init.h> |
| 18 | #include <soc/bootblock.h> |
| 19 | #include <soc/pch.h> |
| 20 | #include <soc/pci_devs.h> |
| 21 | #include <string.h> |
| 22 | |
| 23 | static struct { |
| 24 | u32 cpuid; |
| 25 | const char *name; |
| 26 | } cpu_table[] = { |
| 27 | { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, |
| 28 | }; |
| 29 | |
| 30 | static struct { |
| 31 | u16 mchid; |
| 32 | const char *name; |
| 33 | } mch_table[] = { |
| 34 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, "Alderlake-P" }, |
| 35 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_2, "Alderlake-P" }, |
| 36 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, "Alderlake-P" }, |
| 37 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, "Alderlake-P" }, |
| 38 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, "Alderlake-P" }, |
| 39 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, "Alderlake-P" }, |
| 40 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, "Alderlake-P" }, |
| 41 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_8, "Alderlake-P" }, |
| 42 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" }, |
| 43 | }; |
| 44 | |
| 45 | static struct { |
| 46 | u16 espiid; |
| 47 | const char *name; |
| 48 | } pch_table[] = { |
| 49 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, "Alderlake-P SKU" }, |
| 50 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, "Alderlake-P SKU" }, |
| 51 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, "Alderlake-P SKU" }, |
| 52 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, "Alderlake-P SKU" }, |
| 53 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, "Alderlake-P SKU" }, |
| 54 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, "Alderlake-P SKU" }, |
| 55 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, "Alderlake-P SKU" }, |
| 56 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, "Alderlake-P SKU" }, |
| 57 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, "Alderlake-P SKU" }, |
| 58 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, "Alderlake-P SKU" }, |
| 59 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, "Alderlake-P SKU" }, |
| 60 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, "Alderlake-P SKU" }, |
| 61 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, "Alderlake-P SKU" }, |
| 62 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, "Alderlake-P SKU" }, |
| 63 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, "Alderlake-P SKU" }, |
| 64 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, "Alderlake-P SKU" }, |
| 65 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, "Alderlake-P SKU" }, |
| 66 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, "Alderlake-P SKU" }, |
| 67 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, "Alderlake-P SKU" }, |
| 68 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, "Alderlake-P SKU" }, |
| 69 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, "Alderlake-P SKU" }, |
| 70 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, "Alderlake-P SKU" }, |
| 71 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, "Alderlake-P SKU" }, |
| 72 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, "Alderlake-P SKU" }, |
| 73 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, "Alderlake-P SKU" }, |
| 74 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, "Alderlake-P SKU" }, |
| 75 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, "Alderlake-P SKU" }, |
| 76 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, "Alderlake-P SKU" }, |
| 77 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, "Alderlake-P SKU" }, |
| 78 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" }, |
| 79 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, |
| 80 | { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, |
| 81 | }; |
| 82 | |
| 83 | static struct { |
| 84 | u16 igdid; |
| 85 | const char *name; |
| 86 | } igd_table[] = { |
| 87 | { PCI_DEVICE_ID_INTEL_ADL_GT0, "Alderlake GT0" }, |
| 88 | { PCI_DEVICE_ID_INTEL_ADL_GT1, "Alderlake GT1" }, |
| 89 | { PCI_DEVICE_ID_INTEL_ADL_GT1_1, "Alderlake GT1" }, |
| 90 | { PCI_DEVICE_ID_INTEL_ADL_GT1_2, "Alderlake GT1" }, |
| 91 | { PCI_DEVICE_ID_INTEL_ADL_GT1_3, "Alderlake GT1" }, |
| 92 | { PCI_DEVICE_ID_INTEL_ADL_GT1_4, "Alderlake GT1" }, |
| 93 | { PCI_DEVICE_ID_INTEL_ADL_GT1_5, "Alderlake GT1" }, |
| 94 | { PCI_DEVICE_ID_INTEL_ADL_GT1_6, "Alderlake GT1" }, |
| 95 | { PCI_DEVICE_ID_INTEL_ADL_GT1_7, "Alderlake GT1" }, |
| 96 | { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, |
| 97 | { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, |
| 98 | { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, |
| 99 | }; |
| 100 | |
| 101 | static inline uint8_t get_dev_revision(pci_devfn_t dev) |
| 102 | { |
| 103 | return pci_read_config8(dev, PCI_REVISION_ID); |
| 104 | } |
| 105 | |
| 106 | static inline uint16_t get_dev_id(pci_devfn_t dev) |
| 107 | { |
| 108 | return pci_read_config16(dev, PCI_DEVICE_ID); |
| 109 | } |
| 110 | |
| 111 | static void report_cpu_info(void) |
| 112 | { |
| 113 | u32 i, cpu_id, cpu_feature_flag; |
| 114 | char cpu_name[49]; |
| 115 | int vt, txt, aes; |
| 116 | static const char *const mode[] = {"NOT ", ""}; |
| 117 | const char *cpu_type = "Unknown"; |
| 118 | |
| 119 | fill_processor_name(cpu_name); |
| 120 | cpu_id = cpu_get_cpuid(); |
| 121 | |
| 122 | /* Look for string to match the name */ |
| 123 | for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { |
| 124 | if (cpu_table[i].cpuid == cpu_id) { |
| 125 | cpu_type = cpu_table[i].name; |
| 126 | break; |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); |
| 131 | printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", |
| 132 | cpu_id, cpu_type, get_current_microcode_rev()); |
| 133 | |
| 134 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 135 | aes = !!(cpu_feature_flag & CPUID_AES); |
| 136 | txt = !!(cpu_feature_flag & CPUID_SMX); |
| 137 | vt = !!(cpu_feature_flag & CPUID_VMX); |
| 138 | printk(BIOS_DEBUG, |
| 139 | "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", |
| 140 | mode[aes], mode[txt], mode[vt]); |
| 141 | } |
| 142 | |
| 143 | static void report_mch_info(void) |
| 144 | { |
| 145 | int i; |
| 146 | uint16_t mchid = get_dev_id(SA_DEV_ROOT); |
| 147 | const char *mch_type = "Unknown"; |
| 148 | |
| 149 | for (i = 0; i < ARRAY_SIZE(mch_table); i++) { |
| 150 | if (mch_table[i].mchid == mchid) { |
| 151 | mch_type = mch_table[i].name; |
| 152 | break; |
| 153 | } |
| 154 | } |
| 155 | |
| 156 | printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", |
| 157 | mchid, get_dev_revision(SA_DEV_ROOT), mch_type); |
| 158 | } |
| 159 | |
| 160 | static void report_pch_info(void) |
| 161 | { |
| 162 | int i; |
| 163 | pci_devfn_t dev = PCH_DEV_ESPI; |
| 164 | uint16_t espiid = get_dev_id(dev); |
| 165 | const char *pch_type = "Unknown"; |
| 166 | |
| 167 | for (i = 0; i < ARRAY_SIZE(pch_table); i++) { |
| 168 | if (pch_table[i].espiid == espiid) { |
| 169 | pch_type = pch_table[i].name; |
| 170 | break; |
| 171 | } |
| 172 | } |
| 173 | printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", |
| 174 | espiid, get_dev_revision(dev), pch_type); |
| 175 | } |
| 176 | |
| 177 | static void report_igd_info(void) |
| 178 | { |
| 179 | int i; |
| 180 | pci_devfn_t dev = SA_DEV_IGD; |
| 181 | uint16_t igdid = get_dev_id(dev); |
| 182 | const char *igd_type = "Unknown"; |
| 183 | |
| 184 | for (i = 0; i < ARRAY_SIZE(igd_table); i++) { |
| 185 | if (igd_table[i].igdid == igdid) { |
| 186 | igd_type = igd_table[i].name; |
| 187 | break; |
| 188 | } |
| 189 | } |
| 190 | printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", |
| 191 | igdid, get_dev_revision(dev), igd_type); |
| 192 | } |
| 193 | |
| 194 | void report_platform_info(void) |
| 195 | { |
| 196 | report_cpu_info(); |
| 197 | report_mch_info(); |
| 198 | report_pch_info(); |
| 199 | report_igd_info(); |
| 200 | } |