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review.coreboot.org / coreboot / b3a8cc54dbaf833c590a56f912209a5632b71f49 / . / src / southbridge / nvidia / ck804 / early_setup_car.c
blob: bc1e78111592c626f933c162cba3bf0139187d9d [file] [log] [blame]
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]1/*
Uwe Hermann8af6d552010-10-17 19:13:18 +0000[diff] [blame]2 * This file is part of the coreboot project.
3 *
Timothy Pearsone9162012015-01-23 20:29:46 -0600[diff] [blame]4 * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
5 *
Uwe Hermann8af6d552010-10-17 19:13:18 +0000[diff] [blame]6 * Copyright (C) 2004 Tyan Computer
7 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]17 */
Yinghai Lud4b278c2006-10-04 20:46:15 +0000[diff] [blame]18
Kyösti Mälkki73627682019-03-02 20:16:23 +0200[diff] [blame]19#include <arch/io.h>
Nico Huber718c6fa2018-10-11 22:54:25 +0200[diff] [blame]20#include <southbridge/amd/common/reset.h>
Kyösti Mälkki413e3da2015-02-03 08:05:55 +0200[diff] [blame]21#include "ck804.h"
22
Timothy Pearsone9162012015-01-23 20:29:46 -0600[diff] [blame]23/* Someone messed up and snuck in some K8-specific code */
24static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { return 0; /* stub */};
Timothy Pearsone9162012015-01-23 20:29:46 -0600[diff] [blame]25
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]26static int set_ht_link_ck804(u8 ht_c_num)
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]27{
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]28 unsigned vendorid = 0x10de;
29 unsigned val = 0x01610169;
30 return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]31}
32
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]33static void setup_ss_table(unsigned index, unsigned where, unsigned control,
34 const unsigned int *register_values, int max)
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]35{
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]36 int i;
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]37 unsigned val;
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]38
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]39 val = inl(control);
40 val &= 0xfffffffe;
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]41 outl(val, control);
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]42
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]43 outl(0, index);
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]44
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]45 for (i = 0; i < max; i++) {
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]46 unsigned long reg;
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]47 reg = register_values[i];
48 outl(reg, where);
49 }
50 val = inl(control);
51 val |= 1;
52 outl(val, control);
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]53}
54
55#define ANACTRL_IO_BASE 0x3000
56#define ANACTRL_REG_POS 0x68
57
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]58#define SYSCTRL_IO_BASE 0x2000
59#define SYSCTRL_REG_POS 0x64
60
61/*
Jonathan Kollaschfae0d6c2010-11-21 22:55:46 +0000[diff] [blame]62 * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X.
63 * Apparently some sort of lane configuration.
64 *
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]65 * 16 1 1 2 :0
66 * 8 8 2 2 :1
67 * 8 8 4 :2
68 * 8 4 4 4 :3
69 * 16 4 :4
Jonathan Kollaschfae0d6c2010-11-21 22:55:46 +0000[diff] [blame]70 */
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]71
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]72/* There will be implicit offsets applied, the writes below do not
73 * really happen at the PCI_ADDR() this expands to.
74 */
75#define CK804_DEV(d, f, r) PCI_ADDR(0, d, f, r)
76
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]77static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
78 unsigned *io_base)
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]79{
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]80 static const unsigned int ctrl_devport_conf[] = {
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]81 CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
82 CK804_DEV(0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]83 };
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]84
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]85 int j;
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]86 for (j = 0; j < ck804_num; j++) {
Myles Watson21ee98b2009-10-13 22:53:24 +0000[diff] [blame]87 u32 dev;
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]88 if (busn[j] == 0) /* SB chain */
Myles Watson21ee98b2009-10-13 22:53:24 +0000[diff] [blame]89 dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0);
90 else
91 dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0);
92 setup_resource_map_offset(ctrl_devport_conf,
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]93 ARRAY_SIZE(ctrl_devport_conf), dev, io_base[j]);
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]94 }
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]95}
96
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]97static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
98 unsigned *io_base)
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]99{
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]100 static const unsigned int ctrl_devport_conf_clear[] = {
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]101 CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0,
102 CK804_DEV(0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0,
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]103 };
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]104
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]105 int j;
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]106 for (j = 0; j < ck804_num; j++) {
Myles Watson21ee98b2009-10-13 22:53:24 +0000[diff] [blame]107 u32 dev;
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]108 if (busn[j] == 0) /* SB chain */
Myles Watson21ee98b2009-10-13 22:53:24 +0000[diff] [blame]109 dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0);
110 else
111 dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0);
112 setup_resource_map_offset(ctrl_devport_conf_clear,
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]113 ARRAY_SIZE(ctrl_devport_conf_clear), dev, io_base[j]);
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]114 }
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]115}
116
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]117static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
118 unsigned *io_base)
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]119{
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]120 static const unsigned int ctrl_conf_master[] = {
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]121 RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880,
122 RES_PCI_IO, CK804_DEV(1, 2, 0x90), 0xffff000f, 0x000074a0,
123 RES_PCI_IO, CK804_DEV(1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
124 RES_PCI_IO, CK804_DEV(1, 2, 0xac), 0xffffff00, 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]125
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]126 RES_PCI_IO, CK804_DEV(0, 0, 0x48), 0xfffffffd, 0x00000002,
127 RES_PCI_IO, CK804_DEV(0, 0, 0x74), 0xfffff00f, 0x000009d0,
128 RES_PCI_IO, CK804_DEV(0, 0, 0x8c), 0xffff0000, 0x0000007f,
129 RES_PCI_IO, CK804_DEV(0, 0, 0xcc), 0xfffffff8, 0x00000003,
130 RES_PCI_IO, CK804_DEV(0, 0, 0xd0), 0xff000000, 0x00000000,
131 RES_PCI_IO, CK804_DEV(0, 0, 0xd4), 0xff000000, 0x00000000,
132 RES_PCI_IO, CK804_DEV(0, 0, 0xd8), 0xff000000, 0x00000000,
133 RES_PCI_IO, CK804_DEV(0, 0, 0xdc), 0x7f000000, 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]134
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]135 RES_PCI_IO, CK804_DEV(1, 0, 0xf0), 0xfffffffd, 0x00000002,
136 RES_PCI_IO, CK804_DEV(1, 0, 0xf8), 0xffffffcf, 0x00000010,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]137
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]138 RES_PCI_IO, CK804_DEV(9, 0, 0x40), 0xfff8ffff, 0x00030000,
139 RES_PCI_IO, CK804_DEV(9, 0, 0x4c), 0xfe00ffff, 0x00440000,
140 RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]141
142#ifdef CK804_MB_SETUP
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]143 CK804_MB_SETUP
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]144#endif
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]145
Kyösti Mälkkid840eb52018-05-24 00:34:15 +0300[diff] [blame]146#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
Jonathan A. Kollaschacba73a2015-07-20 09:51:34 -0500[diff] [blame]147 /*
148 * Avoid crash (complete with severe memory corruption!) during initial CAR boot
149 * in ck804_early_setup_x() on Fam10h systems by not touching 0x78.
150 * Interestingly once the system is fully booted into Linux this can be set, but
151 * not before! Apparently something isn't initialized but the amount of effort
152 * required to fix this is non-negligible and of unknown real-world benefit
153 */
154#else
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]155 RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x19000000,
Timothy Pearsone1cc3ab2015-01-24 13:46:46 -0600[diff] [blame]156#endif
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]157 RES_PCI_IO, CK804_DEV(1, 0, 0xe0), 0xfffffeff, 0x00000100,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]158
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]159 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
160 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
161 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
162 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
163 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
164 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]165
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]166 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
167 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
168 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]169
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]170 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]171
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]172 /* Activate master port on primary SATA controller. */
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]173 RES_PCI_IO, CK804_DEV(7, 0, 0x50), ~(0x1f000013), 0x15000013,
174 RES_PCI_IO, CK804_DEV(7, 0, 0x64), ~(0x00000001), 0x00000001,
175 RES_PCI_IO, CK804_DEV(7, 0, 0x68), ~(0x02000000), 0x02000000,
176 RES_PCI_IO, CK804_DEV(7, 0, 0x70), ~(0x000f0000), 0x00040000,
177 RES_PCI_IO, CK804_DEV(7, 0, 0xa0), ~(0x000001ff), 0x00000150,
178 RES_PCI_IO, CK804_DEV(7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
179 RES_PCI_IO, CK804_DEV(7, 0, 0x7c), ~(0x00000010), 0x00000000,
180 RES_PCI_IO, CK804_DEV(7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
181 RES_PCI_IO, CK804_DEV(7, 0, 0xd0), ~(0xf0000000), 0x00000000,
182 RES_PCI_IO, CK804_DEV(7, 0, 0xe0), ~(0xf0000000), 0x00000000,
Myles Watsonb0575d82009-10-14 02:38:24 +0000[diff] [blame]183
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]184 RES_PCI_IO, CK804_DEV(8, 0, 0x50), ~(0x1f000013), 0x15000013,
185 RES_PCI_IO, CK804_DEV(8, 0, 0x64), ~(0x00000001), 0x00000001,
186 RES_PCI_IO, CK804_DEV(8, 0, 0x68), ~(0x02000000), 0x02000000,
187 RES_PCI_IO, CK804_DEV(8, 0, 0x70), ~(0x000f0000), 0x00040000,
188 RES_PCI_IO, CK804_DEV(8, 0, 0xa0), ~(0x000001ff), 0x00000150,
189 RES_PCI_IO, CK804_DEV(8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
190 RES_PCI_IO, CK804_DEV(8, 0, 0x7c), ~(0x00000010), 0x00000000,
191 RES_PCI_IO, CK804_DEV(8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
192 RES_PCI_IO, CK804_DEV(8, 0, 0xd0), ~(0xf0000000), 0x00000000,
193 RES_PCI_IO, CK804_DEV(8, 0, 0xe0), ~(0xf0000000), 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]194
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]195 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]196
Myles Watsonb0575d82009-10-14 02:38:24 +0000[diff] [blame]197 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]198
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]199 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]200
Jonathan Kollaschfae0d6c2010-11-21 22:55:46 +0000[diff] [blame]201 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]202
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]203 /* SYSCTRL */
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]204 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
205 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
Martin Roth1858d6a2017-06-24 21:30:42 -0600[diff] [blame]206#if IS_ENABLED(CONFIG_CK804_USE_NIC)
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]207 RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]208 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
209 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
210 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]211 RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23),
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]212#endif
213
Martin Roth1858d6a2017-06-24 21:30:42 -0600[diff] [blame]214#if IS_ENABLED(CONFIG_CK804_USE_ACI)
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]215 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
216 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]217#endif
Timothy Pearson02112bd2015-01-26 02:15:57 -0600[diff] [blame]218
219#if IS_ENABLED(CONFIG_CK804_PCIE_PME_WAKE)
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]220 RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffffffff, 0x00400000,
Timothy Pearson02112bd2015-01-26 02:15:57 -0600[diff] [blame]221#else
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]222 RES_PCI_IO, CK804_DEV(1, 0, 0xe4), 0xffbfffff, 0x00000000,
Timothy Pearson02112bd2015-01-26 02:15:57 -0600[diff] [blame]223#endif
Myles Watson83768312010-07-06 20:36:36 +0000[diff] [blame]224 };
225
226 static const unsigned int ctrl_conf_multiple[] = {
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]227 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]228 };
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]229
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]230 static const unsigned int ctrl_conf_slave[] = {
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]231 RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880,
232 RES_PCI_IO, CK804_DEV(1, 2, 0x90), 0xffff000f, 0x000074a0,
233 RES_PCI_IO, CK804_DEV(1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]234
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]235 RES_PCI_IO, CK804_DEV(0, 0, 0x48), 0xfffffffd, 0x00000002,
236 RES_PCI_IO, CK804_DEV(0, 0, 0x74), 0xfffff00f, 0x000009d0,
237 RES_PCI_IO, CK804_DEV(0, 0, 0x8c), 0xffff0000, 0x0000007f,
238 RES_PCI_IO, CK804_DEV(0, 0, 0xcc), 0xfffffff8, 0x00000003,
239 RES_PCI_IO, CK804_DEV(0, 0, 0xd0), 0xff000000, 0x00000000,
240 RES_PCI_IO, CK804_DEV(0, 0, 0xd4), 0xff000000, 0x00000000,
241 RES_PCI_IO, CK804_DEV(0, 0, 0xd8), 0xff000000, 0x00000000,
242 RES_PCI_IO, CK804_DEV(0, 0, 0xdc), 0x7f000000, 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]243
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]244 RES_PCI_IO, CK804_DEV(1, 0, 0xf0), 0xfffffffd, 0x00000002,
245 RES_PCI_IO, CK804_DEV(1, 0, 0xf8), 0xffffffcf, 0x00000010,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]246
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]247 RES_PCI_IO, CK804_DEV(9, 0, 0x40), 0xfff8ffff, 0x00030000,
248 RES_PCI_IO, CK804_DEV(9, 0, 0x4c), 0xfe00ffff, 0x00440000,
249 RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]250
Jonathan A. Kollaschacba73a2015-07-20 09:51:34 -0500[diff] [blame]251 /*
252 * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for
253 * non-primary chains too???
254 */
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]255 RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x20000000,
256 RES_PCI_IO, CK804_DEV(1, 0, 0xe0), 0xfffffeff, 0x00000000,
257 RES_PCI_IO, CK804_DEV(1, 0, 0xe8), 0xffffff00, 0x000000ff,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]258
Myles Watson21ee98b2009-10-13 22:53:24 +0000[diff] [blame]259 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
260 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
261 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
262 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
263 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
264 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]265
Myles Watson21ee98b2009-10-13 22:53:24 +0000[diff] [blame]266 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]267
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]268 RES_PCI_IO, CK804_DEV(8, 0, 0x50), ~(0x1f000013), 0x15000013,
269 RES_PCI_IO, CK804_DEV(8, 0, 0x64), ~(0x00000001), 0x00000001,
270 RES_PCI_IO, CK804_DEV(8, 0, 0x68), ~(0x02000000), 0x02000000,
271 RES_PCI_IO, CK804_DEV(8, 0, 0x70), ~(0x000f0000), 0x00040000,
272 RES_PCI_IO, CK804_DEV(8, 0, 0xa0), ~(0x000001ff), 0x00000150,
273 RES_PCI_IO, CK804_DEV(8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
274 RES_PCI_IO, CK804_DEV(8, 0, 0x7c), ~(0x00000010), 0x00000000,
275 RES_PCI_IO, CK804_DEV(8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
276 RES_PCI_IO, CK804_DEV(8, 0, 0xd0), ~(0xf0000000), 0x00000000,
277 RES_PCI_IO, CK804_DEV(8, 0, 0xe0), ~(0xf0000000), 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]278
Myles Watson21ee98b2009-10-13 22:53:24 +0000[diff] [blame]279 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]280
Myles Watsonb0575d82009-10-14 02:38:24 +0000[diff] [blame]281 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]282
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]283 /* This line doesn't exist in the non-CAR version. */
Myles Watson21ee98b2009-10-13 22:53:24 +0000[diff] [blame]284 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]285
Jonathan Kollaschfae0d6c2010-11-21 22:55:46 +0000[diff] [blame]286 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]287
Martin Roth1858d6a2017-06-24 21:30:42 -0600[diff] [blame]288#if IS_ENABLED(CONFIG_CK804_USE_NIC)
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]289 RES_PCI_IO, CK804_DEV(0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]290 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
291 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
292 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
Kyösti Mälkki43997b72019-01-05 14:34:55 +0200[diff] [blame]293 RES_PCI_IO, CK804_DEV(1, 0, 0xe4), ~(1 << 23), (1 << 23),
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]294#endif
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]295 };
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]296
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]297 int j;
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]298 for (j = 0; j < ck804_num; j++) {
299 if (busn[j] == 0) {
300 setup_resource_map_x_offset(ctrl_conf_master,
301 ARRAY_SIZE(ctrl_conf_master),
Myles Watson83768312010-07-06 20:36:36 +0000[diff] [blame]302 PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]);
303 if (ck804_num > 1)
304 setup_resource_map_x_offset(ctrl_conf_multiple,
305 ARRAY_SIZE(ctrl_conf_multiple),
306 PCI_DEV(0, CK804_DEVN_BASE, 0), 0);
307
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]308 continue;
309 }
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]310
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]311 setup_resource_map_x_offset(ctrl_conf_slave,
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]312 ARRAY_SIZE(ctrl_conf_slave),
313 PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]);
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]314 }
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]315
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]316 for (j = 0; j < ck804_num; j++) {
317 /* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */
318 /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */
319 /* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */
320 setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40,
321 io_base[j] + ANACTRL_IO_BASE + 0x44,
322 io_base[j] + ANACTRL_IO_BASE + 0x48,
323 pcie_ss_tbl, 64);
324 setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0,
325 io_base[j] + ANACTRL_IO_BASE + 0xb4,
326 io_base[j] + ANACTRL_IO_BASE + 0xb8,
327 sata_ss_tbl, 64);
Myles Watsonb0575d82009-10-14 02:38:24 +0000[diff] [blame]328 setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0,
329 io_base[j] + ANACTRL_IO_BASE + 0xc4,
330 io_base[j] + ANACTRL_IO_BASE + 0xc8,
331 cpu_ss_tbl, 64);
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]332 }
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]333}
334
335static int ck804_early_setup_x(void)
336{
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]337 unsigned busn[4], io_base[4];
338 int i, ck804_num = 0;
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]339
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]340 for (i = 0; i < 4; i++) {
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]341 u32 id;
Antonello Dettori10505472016-09-03 10:45:33 +0200[diff] [blame]342 pci_devfn_t dev;
Uwe Hermann7e2fbd52011-01-04 17:36:55 +0000[diff] [blame]343 if (i == 0) /* SB chain */
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]344 dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0);
345 else
346 dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0);
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]347 id = pci_read_config32(dev, PCI_VENDOR_ID);
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]348 if (id == 0x005e10de) {
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]349 busn[ck804_num] = i * 0x40;
350 io_base[ck804_num] = i * 0x4000;
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]351 ck804_num++;
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]352 }
353 }
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]354
Timothy Pearsoncdc526e2015-10-28 02:58:37 -0500[diff] [blame]355 printk(BIOS_DEBUG, "ck804_early_set_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]);
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]356 ck804_early_set_port(ck804_num, busn, io_base);
Timothy Pearsoncdc526e2015-10-28 02:58:37 -0500[diff] [blame]357 printk(BIOS_DEBUG, "ck804_early_setup(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]);
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]358 ck804_early_setup(ck804_num, busn, io_base);
Timothy Pearsoncdc526e2015-10-28 02:58:37 -0500[diff] [blame]359 printk(BIOS_DEBUG, "ck804_early_clear_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]);
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]360 ck804_early_clear_port(ck804_num, busn, io_base);
Uwe Hermann7f3d48c2008-10-02 18:19:17 +0000[diff] [blame]361
Yinghai Lu968bbe82005-12-06 23:34:09 +0000[diff] [blame]362 return set_ht_link_ck804(4);
363}
Yinghai Lu9a791df2006-04-03 20:38:34 +0000[diff] [blame]364
Nico Hubere20dd192018-10-07 12:12:27 +0200[diff] [blame]365void do_board_reset(void)
Yinghai Lu9a791df2006-04-03 20:38:34 +0000[diff] [blame]366{
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]367 set_bios_reset();
Yinghai Lu9a791df2006-04-03 20:38:34 +0000[diff] [blame]368
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]369 /* full reset */
370 outb(0x0a, 0x0cf9);
371 outb(0x0e, 0x0cf9);
Yinghai Lu9a791df2006-04-03 20:38:34 +0000[diff] [blame]372}
373
Julius Werner01f9aa52017-05-18 16:03:26 -0700[diff] [blame]374void do_soft_reset(void)
Yinghai Lu9a791df2006-04-03 20:38:34 +0000[diff] [blame]375{
Myles Watson64caf362008-09-18 16:27:00 +0000[diff] [blame]376 set_bios_reset();
377
378 /* link reset */
379 outb(0x02, 0x0cf9);
380 outb(0x06, 0x0cf9);
Yinghai Lu9a791df2006-04-03 20:38:34 +0000[diff] [blame]381}
Timothy Pearson56699942015-10-28 14:41:42 -0500[diff] [blame]382
383void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
384{
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200[diff] [blame]385 /* The default value for CK804 is good. */
386 /* Set VFSMAF (VID/FID System Management Action Field) to 2. */
Martin Rothbb9722b2016-07-28 16:32:56 -0600[diff] [blame]387}