Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <lib.h> |
| 20 | #include <timestamp.h> |
| 21 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 22 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 24 | #include <device/pci_def.h> |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 25 | #include <cpu/x86/lapic.h> |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 26 | #include <cbmem.h> |
| 27 | #include <console/console.h> |
Kyösti Mälkki | 63649d2 | 2018-12-29 09:40:40 +0200 | [diff] [blame] | 28 | #include <console/usb.h> |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 29 | #include <drivers/intel/fsp1_0/fsp_util.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 30 | #include <program_loading.h> |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 31 | #include <northbridge/intel/fsp_rangeley/northbridge.h> |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 32 | #include "southbridge/intel/fsp_rangeley/soc.h" |
| 33 | #include "southbridge/intel/fsp_rangeley/gpio.h" |
| 34 | #include "southbridge/intel/fsp_rangeley/romstage.h" |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 35 | #include <cpu/x86/msr.h> |
| 36 | #include "gpio.h" |
| 37 | |
| 38 | void main(FSP_INFO_HEADER *fsp_info_header) |
| 39 | { |
| 40 | uint32_t fd_mask = 0; |
| 41 | uint32_t *func_dis = (uint32_t *)(DEFAULT_PBASE + PBASE_FUNC_DIS); |
| 42 | |
| 43 | /* |
| 44 | * Do not use the Serial Console before it is setup. |
| 45 | * This causes the I/O to clog and a side effect is |
| 46 | * that the reset button stops functioning. So |
| 47 | * instead just use outb so it doesn't output to the |
| 48 | * console when CONFIG_CONSOLE_POST. |
| 49 | */ |
| 50 | outb(0x40, 0x80); |
| 51 | |
| 52 | timestamp_init(get_initial_timestamp()); |
| 53 | timestamp_add_now(TS_START_ROMSTAGE); |
| 54 | |
| 55 | /* Rangeley UART POR state is enabled */ |
| 56 | console_init(); |
| 57 | post_code(0x41); |
| 58 | |
| 59 | /* Enable GPIOs BAR */ |
| 60 | pci_write_config32(SOC_LPC_DEV, GBASE, DEFAULT_GPIOBASE|0x02); |
| 61 | |
| 62 | early_mainboard_romstage_entry(); |
| 63 | |
| 64 | post_code(0x42); |
| 65 | rangeley_sb_early_initialization(); |
| 66 | |
| 67 | post_code(0x46); |
| 68 | /* Program any required function disables */ |
| 69 | get_func_disables(&fd_mask); |
| 70 | |
| 71 | if (fd_mask != 0) { |
| 72 | write32(func_dis, read32(func_dis) | fd_mask); |
| 73 | /* Ensure posted write hits. */ |
| 74 | read32(func_dis); |
| 75 | } |
| 76 | |
| 77 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 78 | |
| 79 | /* |
| 80 | * Call early init to initialize memory and chipset. This function returns |
| 81 | * to the romstage_main_continue function with a pointer to the HOB |
| 82 | * structure. |
| 83 | */ |
| 84 | post_code(0x47); |
| 85 | printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); |
| 86 | fsp_early_init(fsp_info_header); |
| 87 | die("Uh Oh! fsp_early_init should not return here.\n"); |
| 88 | } |
| 89 | |
| 90 | /******************************************************************************* |
| 91 | * The FSP early_init function returns to this function. |
| 92 | * Memory is setup and the stack is set by the FSP. |
| 93 | */ |
| 94 | void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { |
| 95 | int cbmem_was_initted; |
| 96 | void *cbmem_hob_ptr; |
| 97 | |
| 98 | timestamp_add_now(TS_AFTER_INITRAM); |
| 99 | |
| 100 | post_code(0x48); |
| 101 | printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", |
| 102 | __func__, (u32) status, (u32) hob_list_ptr); |
| 103 | |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 104 | /* FSP reconfigures USB, so reinit it to have debug */ |
Arthur Heymans | adc4753 | 2018-12-28 15:48:58 +0100 | [diff] [blame] | 105 | if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) |
Kyösti Mälkki | 63649d2 | 2018-12-29 09:40:40 +0200 | [diff] [blame] | 106 | usbdebug_hw_init(true); |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 107 | |
| 108 | printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); |
| 109 | |
| 110 | post_code(0x4b); |
| 111 | late_mainboard_romstage_entry(); |
| 112 | |
| 113 | post_code(0x4c); |
| 114 | |
| 115 | /* Decode E0000 and F0000 segment to DRAM */ |
| 116 | sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); |
| 117 | |
| 118 | quick_ram_check(); |
| 119 | post_code(0x4d); |
| 120 | |
| 121 | cbmem_was_initted = !cbmem_recovery(0); |
| 122 | |
| 123 | /* Save the HOB pointer in CBMEM to be used in ramstage*/ |
Martin Roth | 4fb64d0 | 2017-01-10 11:15:13 -0700 | [diff] [blame] | 124 | cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); |
| 125 | if (cbmem_hob_ptr == NULL) |
| 126 | die("Could not allocate cbmem for HOB pointer"); |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 127 | *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; |
| 128 | post_code(0x4e); |
| 129 | |
| 130 | post_code(0x4f); |
| 131 | |
| 132 | /* Load the ramstage. */ |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 133 | run_ramstage(); |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 134 | while (1); |
| 135 | } |
| 136 | |
| 137 | uint64_t get_initial_timestamp(void) |
| 138 | { |
| 139 | return 0; |
| 140 | } |