efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | |
Elyes HAOUAS | e51d731 | 2018-05-19 17:01:24 +0200 | [diff] [blame] | 17 | #include <device/device.h> |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 18 | #include <device/pci.h> /* device_operations */ |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <device/smbus.h> /* smbus_bus_operations */ |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 21 | #include <pc80/mc146818rtc.h> |
Edward O'Callaghan | e61dd0f | 2014-05-06 23:53:09 +1000 | [diff] [blame] | 22 | #include <pc80/i8254.h> |
| 23 | #include <pc80/i8259.h> |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 24 | #include <console/console.h> /* printk */ |
Kyösti Mälkki | e2227a2 | 2014-02-05 13:02:55 +0200 | [diff] [blame] | 25 | #include <device/pci_ehci.h> |
Vladimir Serbinenko | 46a86f2 | 2014-10-08 22:38:54 +0200 | [diff] [blame] | 26 | #include <arch/acpi.h> |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 27 | #include "lpc.h" /* lpc_read_resources */ |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 28 | #include "SbPlatform.h" /* Platform Specific Definitions */ |
| 29 | #include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 30 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 31 | #ifndef _RAMSTAGE_ |
| 32 | #define _RAMSTAGE_ |
| 33 | #endif |
| 34 | static AMDSBCFG sb_late_cfg; //global, init in sb900_cimx_config |
| 35 | static AMDSBCFG *sb_config = &sb_late_cfg; |
| 36 | |
| 37 | |
| 38 | /** |
| 39 | * @brief Entry point of Southbridge CIMx callout |
| 40 | * |
| 41 | * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) |
| 42 | * |
| 43 | * @param[in] func Southbridge CIMx Function ID. |
| 44 | * @param[in] data Southbridge Input Data. |
Martin Roth | 6355cbf | 2015-01-04 15:22:26 -0700 | [diff] [blame] | 45 | * @param[in] config Southbridge configuration structure pointer. |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 46 | * |
| 47 | */ |
Elyes HAOUAS | 251279c | 2018-07-08 12:41:56 +0200 | [diff] [blame] | 48 | u32 sb900_callout_entry(u32 func, u32 data, void *config) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 49 | { |
| 50 | u32 ret = 0; |
| 51 | |
| 52 | printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n"); |
| 53 | switch (func) { |
| 54 | case CB_SBGPP_RESET_ASSERT: |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 55 | break; |
| 56 | |
| 57 | case CB_SBGPP_RESET_DEASSERT: |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 58 | break; |
| 59 | |
| 60 | //- case IMC_FIRMWARE_FAIL: |
| 61 | //- break; |
| 62 | |
| 63 | default: |
| 64 | break; |
| 65 | } |
| 66 | |
| 67 | printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - End.\n"); |
| 68 | return ret; |
| 69 | } |
| 70 | |
| 71 | |
| 72 | static struct pci_operations lops_pci = { |
| 73 | .set_subsystem = 0, |
| 74 | }; |
| 75 | |
Elyes HAOUAS | e51d731 | 2018-05-19 17:01:24 +0200 | [diff] [blame] | 76 | static void lpc_enable_resources(struct device *dev) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 77 | { |
| 78 | |
| 79 | printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n"); |
| 80 | pci_dev_enable_resources(dev); |
| 81 | //lpc_enable_childrens_resources(dev); |
| 82 | printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n"); |
| 83 | } |
| 84 | |
Elyes HAOUAS | e51d731 | 2018-05-19 17:01:24 +0200 | [diff] [blame] | 85 | static void lpc_init(struct device *dev) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 86 | { |
| 87 | printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); |
| 88 | /* SB Configure HPET base and enable bit */ |
| 89 | //- hpetInit(sb_config, &(sb_config->BuildParameters)); |
Gabe Black | 03abaee21 | 2014-04-30 21:31:44 -0700 | [diff] [blame] | 90 | cmos_check_update_date(); |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 91 | |
Mike Loptien | a96d24d | 2013-02-25 10:41:28 -0700 | [diff] [blame] | 92 | /* Initialize the real time clock. |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 93 | * The 0 argument tells cmos_init not to |
Mike Loptien | a96d24d | 2013-02-25 10:41:28 -0700 | [diff] [blame] | 94 | * update CMOS unless it is invalid. |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 95 | * 1 tells cmos_init to always initialize the CMOS. |
Mike Loptien | a96d24d | 2013-02-25 10:41:28 -0700 | [diff] [blame] | 96 | */ |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 97 | cmos_init(0); |
Mike Loptien | a96d24d | 2013-02-25 10:41:28 -0700 | [diff] [blame] | 98 | |
Edward O'Callaghan | e61dd0f | 2014-05-06 23:53:09 +1000 | [diff] [blame] | 99 | setup_i8259(); /* Initialize i8259 pic */ |
| 100 | setup_i8254(); /* Initialize i8254 timers */ |
| 101 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 102 | printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); |
| 103 | } |
| 104 | |
Vladimir Serbinenko | 46a86f2 | 2014-10-08 22:38:54 +0200 | [diff] [blame] | 105 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 106 | { |
| 107 | /* Just a dummy */ |
| 108 | return current; |
| 109 | } |
| 110 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 111 | static struct device_operations lpc_ops = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 112 | .read_resources = lpc_read_resources, |
| 113 | .set_resources = lpc_set_resources, |
| 114 | .enable_resources = lpc_enable_resources, |
| 115 | .init = lpc_init, |
Vladimir Serbinenko | 83f81ca | 2014-11-09 13:30:50 +0100 | [diff] [blame] | 116 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
Vladimir Serbinenko | 46a86f2 | 2014-10-08 22:38:54 +0200 | [diff] [blame] | 117 | .write_acpi_tables = acpi_write_hpet, |
| 118 | #endif |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 119 | .scan_bus = scan_lpc_bus, |
| 120 | .ops_pci = &lops_pci, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 121 | }; |
| 122 | |
| 123 | static const struct pci_driver lpc_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 124 | .ops = &lpc_ops, |
| 125 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 126 | .device = PCI_DEVICE_ID_AMD_SB900_LPC, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | |
| 130 | static void sata_enable_resources(struct device *dev) |
| 131 | { |
| 132 | printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - Start.\n"); |
| 133 | //- sataInitAfterPciEnum(sb_config); |
| 134 | pci_dev_enable_resources(dev); |
| 135 | printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - End.\n"); |
| 136 | } |
| 137 | |
| 138 | static void sata_init(struct device *dev) |
| 139 | { |
| 140 | printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - Start.\n"); |
| 141 | sb_config->StdHeader.Func = SB_MID_POST_INIT; |
| 142 | //- AmdSbDispatcher(sb_config); //sataInitMidPost only |
| 143 | //- commonInitLateBoot(sb_config); |
| 144 | //- sataInitLatePost(sb_config); |
| 145 | printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - End.\n"); |
| 146 | } |
| 147 | |
| 148 | static struct device_operations sata_ops = { |
| 149 | .read_resources = pci_dev_read_resources, |
| 150 | .set_resources = pci_dev_set_resources, |
| 151 | .enable_resources = sata_enable_resources, //pci_dev_enable_resources, |
| 152 | .init = sata_init, |
| 153 | .scan_bus = 0, |
| 154 | .ops_pci = &lops_pci, |
| 155 | }; |
| 156 | |
| 157 | static const struct pci_driver sata_driver __pci_driver = { |
| 158 | .ops = &sata_ops, |
| 159 | .vendor = PCI_VENDOR_ID_AMD, |
| 160 | #if (CONFIG_SATA_CONTROLLER_MODE == 0x0 || CONFIG_SATA_CONTROLLER_MODE == 0x3) |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 161 | .device = PCI_DEVICE_ID_AMD_SB900_SATA, //SATA IDE Mode |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 162 | #endif |
| 163 | #if (CONFIG_SATA_CONTROLLER_MODE == 0x2 || CONFIG_SATA_CONTROLLER_MODE == 0x4) |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 164 | .device = PCI_DEVICE_ID_AMD_SB900_SATA_AHCI, //SATA AHCI Mode |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 165 | #endif |
| 166 | #if (CONFIG_SATA_CONTROLLER_MODE == 0x5 || CONFIG_SATA_CONTROLLER_MODE == 0x6) |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 167 | .device = PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI, //SATA AMDAHCI Mode |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 168 | #endif |
| 169 | #if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x0) |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 170 | .device = PCI_DEVICE_ID_AMD_SB900_SATA_RAID5, //SATA RAID5 Mode |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 171 | #endif |
| 172 | #if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x1) |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 173 | .device = PCI_DEVICE_ID_AMD_SB900_SATA_RAID, //SATA RAID Mode |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 174 | #endif |
| 175 | }; |
| 176 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 177 | static void usb_init(struct device *dev) |
| 178 | { |
| 179 | printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - Start.\n"); |
| 180 | //- usbInitAfterPciInit(sb_config); |
| 181 | //- commonInitLateBoot(sb_config); |
| 182 | printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - End.\n"); |
| 183 | } |
| 184 | |
| 185 | static struct device_operations usb_ops = { |
Kyösti Mälkki | fb387df | 2013-06-07 22:16:52 +0300 | [diff] [blame] | 186 | .read_resources = pci_ehci_read_resources, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 187 | .set_resources = pci_dev_set_resources, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 188 | .enable_resources = pci_dev_enable_resources, |
| 189 | .init = usb_init, |
| 190 | .scan_bus = 0, |
| 191 | .ops_pci = &lops_pci, |
| 192 | }; |
| 193 | |
| 194 | /* |
| 195 | * The pci id of usb ctrl 0 and 1 are the same. |
| 196 | */ |
| 197 | static const struct pci_driver usb_xhci123_driver __pci_driver = { |
| 198 | .ops = &usb_ops, |
| 199 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 200 | .device = PCI_DEVICE_ID_AMD_SB900_USB_16_0, /* XHCI-USB1, XHCI-USB2 */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | static const struct pci_driver usb_ohci123_driver __pci_driver = { |
| 204 | .ops = &usb_ops, |
| 205 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 206 | .device = PCI_DEVICE_ID_AMD_SB900_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 207 | }; |
| 208 | |
| 209 | static const struct pci_driver usb_ehci123_driver __pci_driver = { |
| 210 | .ops = &usb_ops, |
| 211 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 212 | .device = PCI_DEVICE_ID_AMD_SB900_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 213 | }; |
| 214 | |
| 215 | static const struct pci_driver usb_ohci4_driver __pci_driver = { |
| 216 | .ops = &usb_ops, |
| 217 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 218 | .device = PCI_DEVICE_ID_AMD_SB900_USB_20_5, /* OHCI-USB4 */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | |
| 222 | static void azalia_init(struct device *dev) |
| 223 | { |
| 224 | printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - Start.\n"); |
| 225 | //- azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio |
| 226 | printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - End.\n"); |
| 227 | } |
| 228 | |
| 229 | static struct device_operations azalia_ops = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 230 | .read_resources = pci_dev_read_resources, |
| 231 | .set_resources = pci_dev_set_resources, |
| 232 | .enable_resources = pci_dev_enable_resources, |
| 233 | .init = azalia_init, |
| 234 | .scan_bus = 0, |
| 235 | .ops_pci = &lops_pci, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 236 | }; |
| 237 | |
| 238 | static const struct pci_driver azalia_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 239 | .ops = &azalia_ops, |
| 240 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 241 | .device = PCI_DEVICE_ID_AMD_SB900_HDA, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
| 244 | |
| 245 | static void gec_init(struct device *dev) |
| 246 | { |
| 247 | printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - Start.\n"); |
| 248 | //- gecInitAfterPciEnum(sb_config); |
| 249 | //- gecInitLatePost(sb_config); |
| 250 | printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - End.\n"); |
| 251 | } |
| 252 | |
| 253 | static struct device_operations gec_ops = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 254 | .read_resources = pci_dev_read_resources, |
| 255 | .set_resources = pci_dev_set_resources, |
| 256 | .enable_resources = pci_dev_enable_resources, |
| 257 | .init = gec_init, |
| 258 | .scan_bus = 0, |
| 259 | .ops_pci = &lops_pci, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 260 | }; |
| 261 | |
| 262 | static const struct pci_driver gec_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 263 | .ops = &gec_ops, |
| 264 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 265 | .device = PCI_DEVICE_ID_AMD_SB900_GEC, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | |
Elyes HAOUAS | e51d731 | 2018-05-19 17:01:24 +0200 | [diff] [blame] | 269 | static void pcie_init(struct device *dev) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 270 | { |
| 271 | printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n"); |
| 272 | //- sbPcieGppLateInit(sb_config); |
| 273 | printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - End.\n"); |
| 274 | } |
| 275 | |
| 276 | static struct device_operations pci_ops = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 277 | .read_resources = pci_bus_read_resources, |
| 278 | .set_resources = pci_dev_set_resources, |
| 279 | .enable_resources = pci_bus_enable_resources, |
| 280 | .init = pcie_init, |
| 281 | .scan_bus = pci_scan_bridge, |
| 282 | .reset_bus = pci_bus_reset, |
| 283 | .ops_pci = &lops_pci, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 284 | }; |
| 285 | |
| 286 | static const struct pci_driver pci_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 287 | .ops = &pci_ops, |
| 288 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 289 | .device = PCI_DEVICE_ID_AMD_SB900_PCI, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | |
| 293 | struct device_operations bridge_ops = { |
| 294 | .read_resources = pci_bus_read_resources, |
| 295 | .set_resources = pci_dev_set_resources, |
| 296 | .enable_resources = pci_bus_enable_resources, |
| 297 | .init = pcie_init, |
| 298 | .scan_bus = pci_scan_bridge, |
| 299 | .enable = 0, |
| 300 | .reset_bus = pci_bus_reset, |
| 301 | .ops_pci = &lops_pci, |
| 302 | }; |
| 303 | |
| 304 | /* 0:15:0 PCIe PortA */ |
| 305 | static const struct pci_driver PORTA_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 306 | .ops = &bridge_ops, |
| 307 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 308 | .device = PCI_DEVICE_ID_AMD_SB900_PCIEA, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 309 | }; |
| 310 | |
| 311 | /* 0:15:1 PCIe PortB */ |
| 312 | static const struct pci_driver PORTB_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 313 | .ops = &bridge_ops, |
| 314 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 315 | .device = PCI_DEVICE_ID_AMD_SB900_PCIEB, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 316 | }; |
| 317 | |
| 318 | /* 0:15:2 PCIe PortC */ |
| 319 | static const struct pci_driver PORTC_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 320 | .ops = &bridge_ops, |
| 321 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 322 | .device = PCI_DEVICE_ID_AMD_SB900_PCIEC, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 323 | }; |
| 324 | |
| 325 | /* 0:15:3 PCIe PortD */ |
| 326 | static const struct pci_driver PORTD_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 327 | .ops = &bridge_ops, |
| 328 | .vendor = PCI_VENDOR_ID_AMD, |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame] | 329 | .device = PCI_DEVICE_ID_AMD_SB900_PCIED, |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 330 | }; |
| 331 | |
| 332 | |
| 333 | /** |
| 334 | * @brief SB Cimx entry point sbBeforePciInit wrapper |
| 335 | */ |
Elyes HAOUAS | e51d731 | 2018-05-19 17:01:24 +0200 | [diff] [blame] | 336 | static void sb900_enable(struct device *dev) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 337 | { |
| 338 | u8 gpp_port = 0; |
| 339 | struct southbridge_amd_cimx_sb900_config *sb_chip = |
| 340 | (struct southbridge_amd_cimx_sb900_config *)(dev->chip_info); |
| 341 | |
| 342 | sb900_cimx_config(sb_config); |
| 343 | printk(BIOS_DEBUG, "sb900_enable() "); |
| 344 | |
| 345 | /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/ |
| 346 | //- commonInitEarlyBoot(sb_config); |
| 347 | //- commonInitEarlyPost(sb_config); |
| 348 | |
| 349 | switch (dev->path.pci.devfn) { |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 350 | case PCI_DEVFN(0x10, 0): /* XHCI-USB */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 351 | //- usbInitBeforePciEnum(sb_config); // USB POST TIME Only |
| 352 | break; |
| 353 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 354 | case PCI_DEVFN(0x11, 0): /* SATA */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 355 | if (dev->enabled) { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 356 | sb_config->SATAMODE.SataMode.SataController = ENABLED; |
Elyes HAOUAS | 0f8b8d9 | 2019-01-03 10:23:28 +0100 | [diff] [blame] | 357 | if (sb_chip->boot_switch_sata_ide == 1) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 358 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. |
Elyes HAOUAS | 0f8b8d9 | 2019-01-03 10:23:28 +0100 | [diff] [blame] | 359 | else if (sb_chip->boot_switch_sata_ide == 0) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 360 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. |
| 361 | } else { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 362 | sb_config->SATAMODE.SataMode.SataController = DISABLED; |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY |
| 366 | break; |
| 367 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 368 | case PCI_DEVFN(0x12, 0): /* OHCI-USB1 */ |
| 369 | case PCI_DEVFN(0x12, 2): /* EHCI-USB1 */ |
| 370 | case PCI_DEVFN(0x13, 0): /* OHCI-USB2 */ |
| 371 | case PCI_DEVFN(0x13, 2): /* EHCI-USB2 */ |
| 372 | case PCI_DEVFN(0x14, 5): /* OHCI-USB4 */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 373 | //- usbInitBeforePciEnum(sb_config); // USB POST TIME Only |
| 374 | break; |
| 375 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 376 | case PCI_DEVFN(0x14, 0): /* SMBUS */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 377 | break; |
| 378 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 379 | case PCI_DEVFN(0x14, 1): /* IDE */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 380 | if (dev->enabled) { |
| 381 | sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; |
| 382 | } else { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 383 | sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 384 | } |
| 385 | //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY |
| 386 | break; |
| 387 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 388 | case PCI_DEVFN(0x14, 2): /* HDA */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 389 | if (dev->enabled) { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 390 | if (sb_config->AzaliaController == AZALIA_DISABLE) { |
| 391 | sb_config->AzaliaController = AZALIA_AUTO; |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 392 | } |
| 393 | printk(BIOS_DEBUG, "hda enabled\n"); |
| 394 | } else { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 395 | sb_config->AzaliaController = AZALIA_DISABLE; |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 396 | printk(BIOS_DEBUG, "hda disabled\n"); |
| 397 | } |
| 398 | //- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio |
| 399 | break; |
| 400 | |
| 401 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 402 | case PCI_DEVFN(0x14, 3): /* LPC */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 403 | break; |
| 404 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 405 | case PCI_DEVFN(0x14, 4): /* PCI */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 406 | break; |
| 407 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 408 | case PCI_DEVFN(0x14, 6): /* GEC */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 409 | if (dev->enabled) { |
| 410 | sb_config->GecConfig = 0; |
| 411 | printk(BIOS_DEBUG, "gec enabled\n"); |
| 412 | } else { |
| 413 | sb_config->GecConfig = 1; |
| 414 | printk(BIOS_DEBUG, "gec disabled\n"); |
| 415 | } |
| 416 | //- gecInitBeforePciEnum(sb_config); // Init GEC |
| 417 | break; |
| 418 | |
Elyes HAOUAS | 7d1a948 | 2019-01-09 16:31:14 +0100 | [diff] [blame] | 419 | case PCI_DEVFN(0x15, 0): /* PCIe PortA */ |
| 420 | case PCI_DEVFN(0x15, 1): /* PCIe PortB */ |
| 421 | case PCI_DEVFN(0x15, 2): /* PCIe PortC */ |
| 422 | case PCI_DEVFN(0x15, 3): /* PCIe PortD */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 423 | gpp_port = (dev->path.pci.devfn) & 0x03; |
| 424 | if (dev->enabled) { |
| 425 | sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED; |
| 426 | } else { |
| 427 | sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED; |
| 428 | } |
| 429 | |
| 430 | /* |
| 431 | * GPP_CFGMODE_X4000: PortA Lanes[3:0] |
| 432 | * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] |
| 433 | * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 |
| 434 | * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 |
| 435 | */ |
| 436 | if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) { |
| 437 | sb_config->GppLinkConfig = sb_chip->gpp_configuration; |
| 438 | } |
| 439 | |
| 440 | //- sbPcieGppEarlyInit(sb_config); |
| 441 | break; |
| 442 | |
| 443 | default: |
| 444 | break; |
| 445 | } |
| 446 | |
| 447 | /* Special setting ABCFG registers before PCI emulation. */ |
| 448 | //- abSpecialSetBeforePciEnum(sb_config); |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 449 | //- usbDesertPll(sb_config); |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 450 | //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; |
| 451 | //AmdSbDispatcher(sb_config); |
| 452 | } |
| 453 | |
| 454 | struct chip_operations southbridge_amd_cimx_sb900_ops = { |
| 455 | CHIP_NAME("ATI SB900") |
| 456 | .enable_dev = sb900_enable, |
| 457 | }; |