Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 16 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 18 | |
Stefan Reinauer | d1cb0ee | 2011-06-04 10:37:35 -0700 | [diff] [blame] | 19 | static void enable_rom(void) |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 20 | { |
Stefan Reinauer | d1cb0ee | 2011-06-04 10:37:35 -0700 | [diff] [blame] | 21 | u16 word; |
Stefan Reinauer | 44c1d31 | 2011-06-04 10:36:21 -0700 | [diff] [blame] | 22 | u32 dword; |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 23 | pci_devfn_t dev; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 24 | |
Stefan Reinauer | 44c1d31 | 2011-06-04 10:36:21 -0700 | [diff] [blame] | 25 | dev = PCI_DEV(0, 0x14, 0x03); |
| 26 | /* SB800 LPC Bridge 0:20:3:44h. |
| 27 | * BIT6: Port Enable for serial port 0x3f8-0x3ff |
| 28 | * BIT29: Port Enable for KBC port 0x60 and 0x64 |
| 29 | * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 |
| 30 | */ |
| 31 | dword = pci_io_read_config32(dev, 0x44); |
Elyes HAOUAS | 9344bde | 2016-10-02 12:30:06 +0200 | [diff] [blame] | 32 | //dword |= (1<<6) | (1<<29) | (1<<30); |
Stefan Reinauer | 44c1d31 | 2011-06-04 10:36:21 -0700 | [diff] [blame] | 33 | /* Turn on all of LPC IO Port decode enable */ |
| 34 | dword = 0xffffffff; |
| 35 | pci_io_write_config32(dev, 0x44, dword); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 36 | |
Stefan Reinauer | 44c1d31 | 2011-06-04 10:36:21 -0700 | [diff] [blame] | 37 | /* SB800 LPC Bridge 0:20:3:48h. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 38 | * BIT0: Port Enable for SuperIO 0x2E-0x2F |
| 39 | * BIT1: Port Enable for SuperIO 0x4E-0x4F |
Stefan Reinauer | 44c1d31 | 2011-06-04 10:36:21 -0700 | [diff] [blame] | 40 | * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) |
| 41 | * BIT6: Port Enable for RTC IO 0x70-0x73 |
| 42 | * BIT21: Port Enable for Port 0x80 |
| 43 | */ |
| 44 | dword = pci_io_read_config32(dev, 0x48); |
| 45 | dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21); |
| 46 | pci_io_write_config32(dev, 0x48, dword); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 47 | |
Elyes HAOUAS | 1bcd7fc | 2016-07-28 21:20:04 +0200 | [diff] [blame] | 48 | /* Enable ROM access */ |
Stefan Reinauer | 44c1d31 | 2011-06-04 10:36:21 -0700 | [diff] [blame] | 49 | word = pci_io_read_config16(dev, 0x6c); |
Marc Jones | 5a91692 | 2011-07-12 23:02:03 -0600 | [diff] [blame] | 50 | word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6); |
Stefan Reinauer | 44c1d31 | 2011-06-04 10:36:21 -0700 | [diff] [blame] | 51 | pci_io_write_config16(dev, 0x6c, word); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 52 | } |
| 53 | |
Stefan Reinauer | d1cb0ee | 2011-06-04 10:37:35 -0700 | [diff] [blame] | 54 | static void enable_prefetch(void) |
| 55 | { |
| 56 | u32 dword; |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 57 | pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); |
Stefan Reinauer | d1cb0ee | 2011-06-04 10:37:35 -0700 | [diff] [blame] | 58 | |
| 59 | /* Enable PrefetchEnSPIFromHost */ |
| 60 | dword = pci_io_read_config32(dev, 0xb8); |
| 61 | pci_io_write_config32(dev, 0xb8, dword | (1 << 24)); |
| 62 | } |
| 63 | |
| 64 | static void enable_spi_fast_mode(void) |
| 65 | { |
Stefan Reinauer | d1cb0ee | 2011-06-04 10:37:35 -0700 | [diff] [blame] | 66 | u32 dword; |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 67 | pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); |
Stefan Reinauer | d1cb0ee | 2011-06-04 10:37:35 -0700 | [diff] [blame] | 68 | |
| 69 | // set temp MMIO base |
| 70 | volatile u32 *spi_base = (void *)0xa0000000; |
| 71 | u32 save = pci_io_read_config32(dev, 0xa0); |
| 72 | pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); |
| 73 | |
| 74 | // early enable of SPI 33 MHz fast mode read |
Kyösti Mälkki | fbdbcb7 | 2014-01-31 20:32:54 +0200 | [diff] [blame] | 75 | dword = spi_base[3]; |
| 76 | spi_base[3] = (dword & ~(3 << 14)) | (1 << 14); |
Stefan Reinauer | d1cb0ee | 2011-06-04 10:37:35 -0700 | [diff] [blame] | 77 | spi_base[0] = spi_base[0] | (1 << 18); // fast read enable |
| 78 | |
| 79 | pci_io_write_config32(dev, 0xa0, save); |
| 80 | } |
| 81 | |
Scott Duplichan | 4edbe00 | 2011-07-13 17:34:16 -0600 | [diff] [blame] | 82 | static void enable_clocks(void) |
| 83 | { |
| 84 | u8 reg8; |
| 85 | u32 reg32; |
| 86 | volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40); |
| 87 | |
| 88 | // Program AcpiMmioEn to enable MMIO access to MiscCntrl register |
| 89 | outb(0x24, 0xCD6); |
| 90 | reg8 = inb(0xCD7); |
| 91 | reg8 |= 1; |
| 92 | reg8 &= ~(1 << 1); |
| 93 | outb(reg8, 0xCD7); |
| 94 | |
Jens Rottmann | 3914a31 | 2013-02-19 15:01:06 +0100 | [diff] [blame] | 95 | // Program SB800 MiscClkCntrl register to configure clock output on the |
| 96 | // 14M_25M_48M_OSC ball usually used for the Super-I/O. |
| 97 | // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz, |
| 98 | // which is the SB800's power up default. We could switch back to 14 |
| 99 | // in the mainboard's romstage.c, but then the clock frequency would |
| 100 | // change twice. |
Scott Duplichan | 4edbe00 | 2011-07-13 17:34:16 -0600 | [diff] [blame] | 101 | reg32 = *acpi_mmio; |
Jens Rottmann | 3914a31 | 2013-02-19 15:01:06 +0100 | [diff] [blame] | 102 | reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) |
Martin Roth | 083504b | 2017-06-24 21:30:14 -0600 | [diff] [blame] | 103 | #if !IS_ENABLED(CONFIG_SUPERIO_WANTS_14MHZ_CLOCK) |
Jens Rottmann | 3914a31 | 2013-02-19 15:01:06 +0100 | [diff] [blame] | 104 | reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz |
| 105 | #endif |
Scott Duplichan | 4edbe00 | 2011-07-13 17:34:16 -0600 | [diff] [blame] | 106 | *acpi_mmio = reg32; |
| 107 | } |
| 108 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 109 | static void bootblock_southbridge_init(void) |
| 110 | { |
Elyes HAOUAS | 1bcd7fc | 2016-07-28 21:20:04 +0200 | [diff] [blame] | 111 | /* Setup the ROM access for 2M */ |
Stefan Reinauer | d1cb0ee | 2011-06-04 10:37:35 -0700 | [diff] [blame] | 112 | enable_rom(); |
| 113 | enable_prefetch(); |
| 114 | enable_spi_fast_mode(); |
Scott Duplichan | 4edbe00 | 2011-07-13 17:34:16 -0600 | [diff] [blame] | 115 | enable_clocks(); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 116 | } |