Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 6 | * Copyright (C) 2015-2017 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 19 | #include <intelblocks/fast_spi.h> |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 20 | #include <intelblocks/smihandler.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 21 | #include <soc/pm.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 22 | |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 23 | const struct smm_save_state_ops *get_smm_save_state_ops(void) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 24 | { |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 25 | return &em64t101_smm_ops; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 26 | } |
| 27 | |
Subrata Banik | 261b893 | 2017-12-22 13:41:35 +0530 | [diff] [blame] | 28 | void smihandler_soc_check_illegal_access(uint32_t tco_sts) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 29 | { |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 30 | if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) |
| 31 | && fast_spi_wpd_status())) |
| 32 | return; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 33 | |
| 34 | /* |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 35 | * BWE is RW, so the SMI was caused by a |
| 36 | * write to BWE, not by a write to the BIOS |
| 37 | * |
| 38 | * This is the place where we notice someone |
| 39 | * is trying to tinker with the BIOS. We are |
| 40 | * trying to be nice and just ignore it. A more |
| 41 | * resolute answer would be to power down the |
| 42 | * box. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 43 | */ |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 44 | printk(BIOS_DEBUG, "Switching back to RO\n"); |
| 45 | fast_spi_enable_wp(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 46 | } |
| 47 | |
Furquan Shaikh | 8f2eadd | 2017-10-16 22:49:05 -0700 | [diff] [blame] | 48 | /* SMI handlers that should be serviced in SCI mode too. */ |
Subrata Banik | 261b893 | 2017-12-22 13:41:35 +0530 | [diff] [blame] | 49 | uint32_t smihandler_soc_get_sci_mask(void) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 50 | { |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 51 | uint32_t sci_mask = |
| 52 | SMI_HANDLER_SCI_EN(APM_STS_BIT) | |
| 53 | SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 54 | |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 55 | return sci_mask; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 56 | } |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 57 | |
| 58 | const smi_handler_t southbridge_smi[SMI_STS_BITS] = { |
| 59 | [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, |
| 60 | [APM_STS_BIT] = smihandler_southbridge_apmc, |
| 61 | [PM1_STS_BIT] = smihandler_southbridge_pm1, |
| 62 | [GPE0_STS_BIT] = smihandler_southbridge_gpe0, |
| 63 | [GPIO_STS_BIT] = smihandler_southbridge_gpi, |
| 64 | [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, |
| 65 | [MCSMI_STS_BIT] = smihandler_southbridge_mc, |
| 66 | [TCO_STS_BIT] = smihandler_southbridge_tco, |
| 67 | [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, |
| 68 | [MONITOR_STS_BIT] = smihandler_southbridge_monitor, |
| 69 | }; |