blob: 94824569224171302d5e490583f7ea9c2f2a3898 [file] [log] [blame]
Aaron Durbin909c5122015-09-29 17:41:30 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2015 Google Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Aaron Durbin909c5122015-09-29 17:41:30 -050014 */
15
Teo Boon Tiongd8e34b22016-12-28 18:56:26 +080016/* I/O delay between post codes on failure */
17#define LHLT_DELAY 0x50000
Aaron Durbin909c5122015-09-29 17:41:30 -050018
19.text
Aaron Durbinddf4fa02016-04-29 12:43:27 -050020.global car_stage_entry
21car_stage_entry:
Teo Boon Tiongd8e34b22016-12-28 18:56:26 +080022 call romstage_c_entry
23 #include "src/drivers/intel/fsp1_1/after_raminit.S"
24
Aaron Durbin909c5122015-09-29 17:41:30 -050025
26 movb $0x69, %ah
27 jmp .Lhlt
28
29.Lhlt:
30 xchg %al, %ah
31#if IS_ENABLED(CONFIG_POST_IO)
32 outb %al, $CONFIG_POST_IO_PORT
33#else
34 post_code(POST_DEAD_CODE)
35#endif
36 movl $LHLT_DELAY, %ecx
37.Lhlt_Delay:
38 outb %al, $0xED
39 loop .Lhlt_Delay
40 jmp .Lhlt