Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 16 | #include <device/mmio.h> |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 20 | #include <device/pci_def.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <soc/pci_devs.h> |
| 23 | |
| 24 | #define SATA_ABAR_PORT_IMPLEMENTED 0x0c |
| 25 | #define SATA_PCI_CFG_PORT_CTL_STS 0x92 |
| 26 | |
Subrata Banik | 828c39e | 2018-02-06 15:20:19 +0530 | [diff] [blame] | 27 | static void *sata_get_ahci_bar(struct device *dev) |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 28 | { |
| 29 | uintptr_t bar; |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 30 | |
| 31 | bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 32 | return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); |
| 33 | } |
| 34 | |
| 35 | /* |
| 36 | * SATA Port control and Status. By default, the SATA ports are set (by HW) |
| 37 | * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial |
| 38 | * power on reset. When enabled by software as per SATA port mapping, |
| 39 | * the ports can transition between the on, partial and slumber states |
| 40 | * and can detect devices. When disabled, the port is in the off state and |
| 41 | * can't detect any devices. |
| 42 | */ |
Subrata Banik | 828c39e | 2018-02-06 15:20:19 +0530 | [diff] [blame] | 43 | static void sata_final(struct device *dev) |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 44 | { |
Subrata Banik | 828c39e | 2018-02-06 15:20:19 +0530 | [diff] [blame] | 45 | void *ahcibar = sata_get_ahci_bar(dev); |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 46 | u32 port_impl, temp; |
| 47 | |
Kane Chen | f73bc0b | 2017-10-05 10:17:07 +0800 | [diff] [blame] | 48 | /* Set Bus Master */ |
| 49 | temp = pci_read_config32(dev, PCI_COMMAND); |
| 50 | pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); |
| 51 | |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 52 | /* Read Ports Implemented (GHC_PI) */ |
Subrata Banik | 828c39e | 2018-02-06 15:20:19 +0530 | [diff] [blame] | 53 | port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); |
| 54 | |
| 55 | if (IS_ENABLED(CONFIG_SOC_AHCI_PORT_IMPLEMENTED_INVERT)) |
| 56 | port_impl = ~port_impl; |
| 57 | |
| 58 | port_impl &= 0x07; /* bit 0-2 */ |
| 59 | |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 60 | /* Port enable */ |
| 61 | temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS); |
| 62 | temp |= port_impl; |
| 63 | pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); |
| 64 | } |
| 65 | |
| 66 | static struct device_operations sata_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 67 | .read_resources = pci_dev_read_resources, |
| 68 | .set_resources = pci_dev_set_resources, |
| 69 | .enable_resources = pci_dev_enable_resources, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 70 | .final = sata_final, |
| 71 | .ops_pci = &pci_dev_ops_pci, |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | static const unsigned short pci_device_ids[] = { |
| 75 | PCI_DEVICE_ID_INTEL_SPT_U_SATA, |
| 76 | PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA, |
| 77 | PCI_DEVICE_ID_INTEL_SPT_KBL_SATA, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 78 | PCI_DEVICE_ID_INTEL_CNL_SATA, |
| 79 | PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 80 | PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA, |
Maulik | fc19ab5 | 2018-01-05 22:40:35 +0530 | [diff] [blame] | 81 | PCI_DEVICE_ID_INTEL_CNP_H_SATA, |
| 82 | PCI_DEVICE_ID_INTEL_CNP_LP_SATA, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 83 | PCI_DEVICE_ID_INTEL_ICP_U_SATA, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 84 | PCI_DEVICE_ID_INTEL_CMP_SATA, |
| 85 | PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, |
| 86 | PCI_DEVICE_ID_INTEL_CMP_LP_SATA, |
Aamir Bohra | 1b1ecae | 2017-05-17 15:12:10 +0530 | [diff] [blame] | 87 | 0 |
| 88 | }; |
| 89 | |
| 90 | static const struct pci_driver pch_sata __pci_driver = { |
| 91 | .ops = &sata_ops, |
| 92 | .vendor = PCI_VENDOR_ID_INTEL, |
| 93 | .devices = pci_device_ids, |
| 94 | }; |