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Subrata Banik03e971c2017-03-07 14:02:23 +05301/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <cpu/x86/mtrr.h>
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020018#include <cpu/x86/msr.h>
Subrata Banik03e971c2017-03-07 14:02:23 +053019#include <cpu/x86/cr.h>
20#include <intelblocks/msr.h>
21
22.text
23.global chipset_teardown_car
24chipset_teardown_car:
25
Aaron Durbinf8744422018-04-18 16:32:30 -060026#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
27 /*
28 * Since Page table is located in CAR, disable paging before CAR
29 * teardown. Also clear CR3 and CR4.PAE.
30 */
31 mov %cr0, %eax
32 and $(~(CR0_PG)), %eax
33 mov %eax, %cr0
34 xor %eax, %eax
35 mov %eax, %cr3
36 mov %cr4, %eax
37 and $(~(CR4_PAE)), %eax
38 mov %eax, %cr4
39#endif
40
Subrata Banik03e971c2017-03-07 14:02:23 +053041 /*
42 * Retrieve return address from stack as it will get trashed below if
43 * execution is utilizing the cache-as-ram stack.
44 */
45 pop %ebx
46
47 /* Disable MTRRs. */
48 mov $(MTRR_DEF_TYPE_MSR), %ecx
49 rdmsr
50 and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
51 wrmsr
52
53#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
54.global car_nem_teardown
55car_nem_teardown:
56
57 /* invalidate cache contents. */
58 invd
59
60 /* Knock down bit 1 then bit 0 of NEM control not combining steps. */
61 mov $(MSR_EVICT_CTL), %ecx
62 rdmsr
63 and $(~(1 << 1)), %eax
64 wrmsr
65 and $(~(1 << 0)), %eax
66 wrmsr
67
68#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
69.global car_cqos_teardown
70car_cqos_teardown:
71
72 /* Go back to all-evicting mode, set both masks to all-1s */
73 mov $MSR_L2_QOS_MASK(0), %ecx
74 rdmsr
75 mov $~0, %al
76 wrmsr
77
78 mov $MSR_L2_QOS_MASK(1), %ecx
79 rdmsr
80 mov $~0, %al
81 wrmsr
82
83 /* Reset CLOS selector to 0 */
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +020084 mov $IA32_PQR_ASSOC, %ecx
Subrata Banik03e971c2017-03-07 14:02:23 +053085 rdmsr
86 and $~IA32_PQR_ASSOC_MASK, %edx
87 wrmsr
88
89#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
90.global car_nem_enhanced_teardown
91car_nem_enhanced_teardown:
92
93 /* invalidate cache contents. */
94 invd
95
96 /* Knock down bit 1 then bit 0 of NEM control not combining steps. */
97 mov $(MSR_EVICT_CTL), %ecx
98 rdmsr
99 and $(~(1 << 1)), %eax
100 wrmsr
101 and $(~(1 << 0)), %eax
102 wrmsr
103
104 /* Reset CLOS selector to 0 */
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +0200105 mov $IA32_PQR_ASSOC, %ecx
Subrata Banik03e971c2017-03-07 14:02:23 +0530106 rdmsr
107 and $~IA32_PQR_ASSOC_MASK, %edx
108 wrmsr
109#endif
110
111 /* Return to caller. */
112 jmp *%ebx