Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2018 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <assert.h> |
| 17 | #include <chip.h> |
| 18 | #include <console/console.h> |
| 19 | #include <fsp/util.h> |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 20 | #include <intelblocks/pmclib.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 21 | #include <soc/iomap.h> |
| 22 | #include <soc/pci_devs.h> |
| 23 | #include <soc/romstage.h> |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 24 | #include <vendorcode/google/chromeos/chromeos.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 25 | |
| 26 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) |
| 27 | { |
| 28 | unsigned int i; |
| 29 | uint32_t mask = 0; |
Lijian Zhao | fe701ee | 2018-10-25 09:29:10 -0700 | [diff] [blame] | 30 | const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 31 | |
| 32 | /* Set IGD stolen size to 64MB. */ |
| 33 | m_cfg->IgdDvmt50PreAlloc = 2; |
| 34 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 35 | m_cfg->IedSize = CONFIG_IED_REGION_SIZE; |
| 36 | m_cfg->SaGv = config->SaGv; |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 37 | if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)) |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 38 | m_cfg->UserBd = BOARD_TYPE_DESKTOP; |
| 39 | else |
| 40 | m_cfg->UserBd = BOARD_TYPE_ULT_ULX; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 41 | m_cfg->RMT = config->RMT; |
| 42 | |
| 43 | for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { |
| 44 | if (config->PcieRpEnable[i]) |
| 45 | mask |= (1 << i); |
| 46 | } |
| 47 | m_cfg->PcieRpEnableMask = mask; |
| 48 | m_cfg->PrmrrSize = config->PrmrrSize; |
| 49 | m_cfg->EnableC6Dram = config->enable_c6dram; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 50 | m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 51 | /* Disable Vmx if Vt-d is already disabled */ |
| 52 | if (config->VtdDisable) |
| 53 | m_cfg->VmxEnable = 0; |
| 54 | else |
| 55 | m_cfg->VmxEnable = config->VmxEnable; |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 56 | #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 57 | m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); |
| 58 | #endif |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 59 | |
| 60 | /* Disable CPU Flex Ratio and SaGv in recovery mode */ |
| 61 | if (vboot_recovery_mode_enabled()) { |
| 62 | struct chipset_power_state *ps = pmc_get_power_state(); |
| 63 | |
| 64 | /* |
| 65 | * Only disable when coming from S5 (cold reset) otherwise |
| 66 | * the flex ratio may be locked and FSP will return an error. |
| 67 | */ |
| 68 | if (ps && ps->prev_sleep_state == ACPI_S5) { |
| 69 | m_cfg->CpuRatio = 0; |
| 70 | m_cfg->SaGv = 0; |
| 71 | } |
| 72 | } |
| 73 | |
Lijian Zhao | fe701ee | 2018-10-25 09:29:10 -0700 | [diff] [blame] | 74 | /* If ISH is enabled, enable ISH elements */ |
| 75 | if (!dev) |
| 76 | m_cfg->PchIshEnable = 0; |
| 77 | else |
| 78 | m_cfg->PchIshEnable = dev->enabled; |
Lijian Zhao | 3ef7449 | 2018-12-06 17:29:55 -0800 | [diff] [blame] | 79 | |
| 80 | /* If HDA is enabled, enable HDA elements */ |
| 81 | dev = dev_find_slot(0, PCH_DEVFN_HDA); |
| 82 | if (!dev) |
| 83 | m_cfg->PchHdaEnable = 0; |
| 84 | else |
| 85 | m_cfg->PchHdaEnable = dev->enabled; |
| 86 | |
V Sowmya | 0bc3e3d | 2019-01-07 13:11:29 +0530 | [diff] [blame] | 87 | /* Enable IPU only if the device is enabled */ |
| 88 | m_cfg->SaIpuEnable = 0; |
| 89 | dev = pcidev_path_on_root(SA_DEVFN_IPU); |
| 90 | if (dev) |
| 91 | m_cfg->SaIpuEnable = dev->enabled; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 95 | { |
| 96 | const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); |
Duncan Laurie | 25b387a | 2018-11-08 15:48:14 -0700 | [diff] [blame] | 97 | const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 98 | assert(dev != NULL); |
| 99 | const config_t *config = dev->chip_info; |
| 100 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 101 | |
| 102 | soc_memory_init_params(m_cfg, config); |
| 103 | |
| 104 | /* Enable SMBus controller based on config */ |
Duncan Laurie | 25b387a | 2018-11-08 15:48:14 -0700 | [diff] [blame] | 105 | if (!smbus) |
| 106 | m_cfg->SmbusEnable = 0; |
| 107 | else |
| 108 | m_cfg->SmbusEnable = smbus->enabled; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 109 | /* Set debug probe type */ |
| 110 | m_cfg->PlatformDebugConsent = config->DebugConsent; |
| 111 | |
| 112 | mainboard_memory_init_params(mupd); |
| 113 | } |
| 114 | |
| 115 | __weak void mainboard_memory_init_params(FSPM_UPD *mupd) |
| 116 | { |
| 117 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 118 | } |