Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lijian Zhao | 0f5d7b9 | 2018-10-05 10:31:11 -0700 | [diff] [blame] | 4 | * Copyright (C) 2017-2018 Intel Corporation. |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 16 | #include <arch/cpu.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <chip.h> |
| 20 | #include <cpu/x86/lapic.h> |
| 21 | #include <cpu/x86/mp.h> |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 22 | #include <cpu/x86/msr.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 23 | #include <cpu/intel/turbo.h> |
| 24 | #include <intelblocks/cpulib.h> |
| 25 | #include <intelblocks/mp_init.h> |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 26 | #include <intelblocks/smm.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 27 | #include <romstage_handoff.h> |
| 28 | #include <soc/cpu.h> |
| 29 | #include <soc/msr.h> |
| 30 | #include <soc/pci_devs.h> |
Subrata Banik | 47a655c | 2017-12-14 18:22:13 +0530 | [diff] [blame] | 31 | #include <soc/pm.h> |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 32 | #include <soc/smm.h> |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 33 | #include <soc/systemagent.h> |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 34 | #include <cpu/x86/mtrr.h> |
| 35 | #include <cpu/intel/microcode.h> |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 36 | |
| 37 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 38 | static const u8 power_limit_time_sec_to_msr[] = { |
| 39 | [0] = 0x00, |
| 40 | [1] = 0x0a, |
| 41 | [2] = 0x0b, |
| 42 | [3] = 0x4b, |
| 43 | [4] = 0x0c, |
| 44 | [5] = 0x2c, |
| 45 | [6] = 0x4c, |
| 46 | [7] = 0x6c, |
| 47 | [8] = 0x0d, |
| 48 | [10] = 0x2d, |
| 49 | [12] = 0x4d, |
| 50 | [14] = 0x6d, |
| 51 | [16] = 0x0e, |
| 52 | [20] = 0x2e, |
| 53 | [24] = 0x4e, |
| 54 | [28] = 0x6e, |
| 55 | [32] = 0x0f, |
| 56 | [40] = 0x2f, |
| 57 | [48] = 0x4f, |
| 58 | [56] = 0x6f, |
| 59 | [64] = 0x10, |
| 60 | [80] = 0x30, |
| 61 | [96] = 0x50, |
| 62 | [112] = 0x70, |
| 63 | [128] = 0x11, |
| 64 | }; |
| 65 | |
| 66 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 67 | static const u8 power_limit_time_msr_to_sec[] = { |
| 68 | [0x00] = 0, |
| 69 | [0x0a] = 1, |
| 70 | [0x0b] = 2, |
| 71 | [0x4b] = 3, |
| 72 | [0x0c] = 4, |
| 73 | [0x2c] = 5, |
| 74 | [0x4c] = 6, |
| 75 | [0x6c] = 7, |
| 76 | [0x0d] = 8, |
| 77 | [0x2d] = 10, |
| 78 | [0x4d] = 12, |
| 79 | [0x6d] = 14, |
| 80 | [0x0e] = 16, |
| 81 | [0x2e] = 20, |
| 82 | [0x4e] = 24, |
| 83 | [0x6e] = 28, |
| 84 | [0x0f] = 32, |
| 85 | [0x2f] = 40, |
| 86 | [0x4f] = 48, |
| 87 | [0x6f] = 56, |
| 88 | [0x10] = 64, |
| 89 | [0x30] = 80, |
| 90 | [0x50] = 96, |
| 91 | [0x70] = 112, |
| 92 | [0x11] = 128, |
| 93 | }; |
| 94 | |
| 95 | /* |
| 96 | * Configure processor power limits if possible |
| 97 | * This must be done AFTER set of BIOS_RESET_CPL |
| 98 | */ |
| 99 | void set_power_limits(u8 power_limit_1_time) |
| 100 | { |
| 101 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 102 | msr_t limit; |
| 103 | unsigned int power_unit; |
| 104 | unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; |
| 105 | u8 power_limit_1_val; |
| 106 | struct device *dev = SA_DEV_ROOT; |
| 107 | config_t *conf = dev->chip_info; |
| 108 | |
| 109 | if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) |
| 110 | power_limit_1_time = 28; |
| 111 | |
| 112 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 113 | return; |
| 114 | |
| 115 | /* Get units */ |
| 116 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 117 | power_unit = 1 << (msr.lo & 0xf); |
| 118 | |
| 119 | /* Get power defaults for this SKU */ |
| 120 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 121 | tdp = msr.lo & 0x7fff; |
| 122 | min_power = (msr.lo >> 16) & 0x7fff; |
| 123 | max_power = msr.hi & 0x7fff; |
| 124 | max_time = (msr.hi >> 16) & 0x7f; |
| 125 | |
| 126 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 127 | |
| 128 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 129 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 130 | |
| 131 | if (min_power > 0 && tdp < min_power) |
| 132 | tdp = min_power; |
| 133 | |
| 134 | if (max_power > 0 && tdp > max_power) |
| 135 | tdp = max_power; |
| 136 | |
| 137 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 138 | |
| 139 | /* Set long term power limit to TDP */ |
| 140 | limit.lo = 0; |
| 141 | tdp_pl1 = ((conf->tdp_pl1_override == 0) ? |
| 142 | tdp : (conf->tdp_pl1_override * power_unit)); |
| 143 | limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); |
| 144 | |
| 145 | /* Set PL1 Pkg Power clamp bit */ |
| 146 | limit.lo |= PKG_POWER_LIMIT_CLAMP; |
| 147 | |
| 148 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 149 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 150 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 151 | |
| 152 | /* Set short term power limit to 1.25 * TDP if no config given */ |
| 153 | limit.hi = 0; |
| 154 | tdp_pl2 = (conf->tdp_pl2_override == 0) ? |
| 155 | (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); |
| 156 | printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit); |
| 157 | limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; |
| 158 | limit.hi |= PKG_POWER_LIMIT_CLAMP; |
| 159 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 160 | |
| 161 | /* Power limit 2 time is only programmable on server SKU */ |
| 162 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 163 | |
| 164 | /* Set PL2 power limit values in MCHBAR and disable PL1 */ |
| 165 | MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); |
| 166 | MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; |
| 167 | |
| 168 | /* Set PsysPl2 */ |
| 169 | if (conf->tdp_psyspl2) { |
| 170 | limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); |
| 171 | limit.hi = 0; |
| 172 | printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", |
| 173 | conf->tdp_psyspl2); |
| 174 | limit.hi |= (conf->tdp_psyspl2 * power_unit) & |
| 175 | PKG_POWER_LIMIT_MASK; |
| 176 | limit.hi |= PKG_POWER_LIMIT_CLAMP; |
| 177 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 178 | |
| 179 | wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); |
| 180 | } |
| 181 | |
| 182 | /* Set PsysPl3 */ |
| 183 | if (conf->tdp_psyspl3) { |
| 184 | limit = rdmsr(MSR_PL3_CONTROL); |
| 185 | limit.lo = 0; |
| 186 | printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", |
| 187 | conf->tdp_psyspl3); |
| 188 | limit.lo |= (conf->tdp_psyspl3 * power_unit) & |
| 189 | PKG_POWER_LIMIT_MASK; |
| 190 | /* Enable PsysPl3 */ |
| 191 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 192 | /* set PsysPl3 time window */ |
| 193 | limit.lo |= (conf->tdp_psyspl3_time & |
| 194 | PKG_POWER_LIMIT_TIME_MASK) << |
| 195 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 196 | /* set PsysPl3 duty cycle */ |
| 197 | limit.lo |= (conf->tdp_psyspl3_dutycycle & |
| 198 | PKG_POWER_LIMIT_DUTYCYCLE_MASK) << |
| 199 | PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; |
| 200 | wrmsr(MSR_PL3_CONTROL, limit); |
| 201 | } |
| 202 | |
| 203 | /* Set Pl4 */ |
| 204 | if (conf->tdp_pl4) { |
| 205 | limit = rdmsr(MSR_VR_CURRENT_CONFIG); |
| 206 | limit.lo = 0; |
| 207 | printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", |
| 208 | conf->tdp_pl4); |
| 209 | limit.lo |= (conf->tdp_pl4 * power_unit) & |
| 210 | PKG_POWER_LIMIT_MASK; |
| 211 | wrmsr(MSR_VR_CURRENT_CONFIG, limit); |
| 212 | } |
| 213 | |
| 214 | /* Set DDR RAPL power limit by copying from MMIO to MSR */ |
| 215 | msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); |
| 216 | msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); |
| 217 | wrmsr(MSR_DDR_RAPL_LIMIT, msr); |
| 218 | |
| 219 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 220 | if (cpu_config_tdp_levels()) { |
| 221 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 222 | limit.hi = 0; |
| 223 | limit.lo = cpu_get_tdp_nominal_ratio(); |
| 224 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 225 | } |
| 226 | } |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 227 | |
| 228 | static void soc_fsp_load(void) |
| 229 | { |
| 230 | fsps_load(romstage_handoff_is_resume()); |
| 231 | } |
| 232 | |
| 233 | static void configure_isst(void) |
| 234 | { |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 235 | struct device *dev = SA_DEV_ROOT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 236 | config_t *conf = dev->chip_info; |
| 237 | msr_t msr; |
| 238 | |
Pratik Prajapati | 41169de | 2019-01-11 13:44:36 -0800 | [diff] [blame] | 239 | if (conf && conf->speed_shift_enable) { |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 240 | /* |
| 241 | * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP |
| 242 | * is supported or not. coreboot needs to configure MSR 0x1AA |
| 243 | * which is then reflected in the CPUID register. |
| 244 | */ |
| 245 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 246 | msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ |
| 247 | msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ |
| 248 | msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ |
| 249 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 250 | } else { |
| 251 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 252 | msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ |
| 253 | msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ |
| 254 | msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ |
| 255 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | static void configure_misc(void) |
| 260 | { |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 261 | struct device *dev = SA_DEV_ROOT; |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 262 | if (!dev) { |
| 263 | printk(BIOS_ERR, "SA_DEV_ROOT device not found!\n"); |
| 264 | return; |
| 265 | } |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 266 | config_t *conf = dev->chip_info; |
| 267 | msr_t msr; |
| 268 | |
| 269 | msr = rdmsr(IA32_MISC_ENABLE); |
| 270 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 271 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Pratik Prajapati | 41169de | 2019-01-11 13:44:36 -0800 | [diff] [blame] | 272 | if (conf && conf->eist_enable) |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 273 | cpu_enable_eist(); |
| 274 | else |
| 275 | cpu_disable_eist(); |
| 276 | wrmsr(IA32_MISC_ENABLE, msr); |
| 277 | |
| 278 | /* Disable Thermal interrupts */ |
| 279 | msr.lo = 0; |
| 280 | msr.hi = 0; |
| 281 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 282 | |
| 283 | /* Enable package critical interrupt only */ |
| 284 | msr.lo = 1 << 4; |
| 285 | msr.hi = 0; |
| 286 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 287 | |
| 288 | /* Enable PROCHOT */ |
| 289 | msr = rdmsr(MSR_POWER_CTL); |
| 290 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ |
| 291 | msr.lo |= (1 << 23); /* Lock it */ |
| 292 | wrmsr(MSR_POWER_CTL, msr); |
| 293 | } |
| 294 | |
| 295 | static void enable_lapic_tpr(void) |
| 296 | { |
| 297 | msr_t msr; |
| 298 | |
| 299 | msr = rdmsr(MSR_PIC_MSG_CONTROL); |
| 300 | msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ |
| 301 | wrmsr(MSR_PIC_MSG_CONTROL, msr); |
| 302 | } |
| 303 | |
| 304 | static void configure_dca_cap(void) |
| 305 | { |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 306 | uint32_t feature_flag; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 307 | msr_t msr; |
| 308 | |
| 309 | /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 310 | feature_flag = cpu_get_feature_flags_ecx(); |
| 311 | if (feature_flag & CPUID_DCA) { |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 312 | msr = rdmsr(IA32_PLATFORM_DCA_CAP); |
| 313 | msr.lo |= 1; |
| 314 | wrmsr(IA32_PLATFORM_DCA_CAP, msr); |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | static void set_energy_perf_bias(u8 policy) |
| 319 | { |
| 320 | msr_t msr; |
| 321 | int ecx; |
| 322 | |
| 323 | /* Determine if energy efficient policy is supported. */ |
| 324 | ecx = cpuid_ecx(0x6); |
| 325 | if (!(ecx & (1 << 3))) |
| 326 | return; |
| 327 | |
| 328 | /* Energy Policy is bits 3:0 */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 329 | msr = rdmsr(IA32_ENERGY_PERF_BIAS); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 330 | msr.lo &= ~0xf; |
| 331 | msr.lo |= policy & 0xf; |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 332 | wrmsr(IA32_ENERGY_PERF_BIAS, msr); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 333 | } |
| 334 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 335 | static void configure_c_states(void) |
| 336 | { |
| 337 | msr_t msr; |
| 338 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 339 | /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ |
| 340 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 341 | msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 342 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
| 343 | |
| 344 | /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ |
| 345 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 346 | msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 347 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
| 348 | |
| 349 | /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| 350 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 351 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 352 | C_STATE_LATENCY_CONTROL_3_LIMIT; |
| 353 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
| 354 | |
| 355 | /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| 356 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 357 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 358 | C_STATE_LATENCY_CONTROL_4_LIMIT; |
| 359 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| 360 | |
| 361 | /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| 362 | msr.hi = 0; |
Vaibhav Shankar | 66dbb0c | 2018-01-11 10:27:50 -0800 | [diff] [blame] | 363 | msr.lo = IRTL_VALID | IRTL_32768_NS | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 364 | C_STATE_LATENCY_CONTROL_5_LIMIT; |
| 365 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
| 366 | } |
| 367 | |
John Su | 3126964 | 2019-01-10 14:53:26 +0800 | [diff] [blame] | 368 | static void configure_thermal_target(void) |
| 369 | { |
| 370 | struct device *dev = SA_DEV_ROOT; |
| 371 | config_t *conf = dev->chip_info; |
| 372 | msr_t msr; |
| 373 | |
| 374 | /* Set TCC activation offset if supported */ |
| 375 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 376 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 377 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 378 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 379 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 380 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 381 | } |
| 382 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 383 | msr.lo &= ~0x7f; /* Bits 6:0 */ |
| 384 | msr.lo |= 0xe6; /* setting 100ms thermal time window */ |
| 385 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 386 | } |
| 387 | |
Lijian Zhao | 0f5d7b9 | 2018-10-05 10:31:11 -0700 | [diff] [blame] | 388 | /* |
| 389 | * The emulated ACPI timer allows replacing of the ACPI timer |
| 390 | * (PM1_TMR) to have no impart on the system. |
| 391 | */ |
| 392 | static void enable_pm_timer_emulation(void) |
| 393 | { |
| 394 | /* ACPI PM timer emulation */ |
| 395 | msr_t msr; |
| 396 | /* |
| 397 | * The derived frequency is calculated as follows: |
| 398 | * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. |
| 399 | * Back solve the multiplier so the 3.579545MHz ACPI timer |
| 400 | * frequency is used. |
| 401 | */ |
| 402 | msr.hi = (3579545ULL << 32) / CTC_FREQ; |
| 403 | /* Set PM1 timer IO port and enable*/ |
| 404 | msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | |
| 405 | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); |
Elyes HAOUAS | f212cf3 | 2018-12-18 10:24:55 +0100 | [diff] [blame] | 406 | wrmsr(MSR_EMULATE_PM_TIMER, msr); |
Lijian Zhao | 0f5d7b9 | 2018-10-05 10:31:11 -0700 | [diff] [blame] | 407 | } |
| 408 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 409 | /* All CPUs including BSP will run the following function. */ |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 410 | void soc_core_init(struct device *cpu) |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 411 | { |
| 412 | /* Clear out pending MCEs */ |
Pratik Prajapati | 2ad1ddb | 2017-08-28 12:28:24 -0700 | [diff] [blame] | 413 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 414 | * of these banks are core vs package scope. For now every CPU clears |
| 415 | * every bank. */ |
Pratik Prajapati | 35cb785 | 2018-05-18 18:05:18 -0700 | [diff] [blame] | 416 | mca_configure(NULL); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 417 | |
| 418 | /* Enable the local CPU apics */ |
| 419 | enable_lapic_tpr(); |
| 420 | setup_lapic(); |
| 421 | |
| 422 | /* Configure c-state interrupt response time */ |
| 423 | configure_c_states(); |
| 424 | |
| 425 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 426 | configure_misc(); |
| 427 | |
| 428 | /* Configure Intel Speed Shift */ |
| 429 | configure_isst(); |
| 430 | |
Lijian Zhao | 0f5d7b9 | 2018-10-05 10:31:11 -0700 | [diff] [blame] | 431 | /* Enable ACPI Timer Emulation via MSR 0x121 */ |
| 432 | enable_pm_timer_emulation(); |
| 433 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 434 | /* Enable Direct Cache Access */ |
| 435 | configure_dca_cap(); |
| 436 | |
| 437 | /* Set energy policy */ |
| 438 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 439 | |
| 440 | /* Enable Turbo */ |
| 441 | enable_turbo(); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 442 | } |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 443 | |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 444 | static void per_cpu_smm_trigger(void) |
| 445 | { |
| 446 | /* Relocate the SMM handler. */ |
| 447 | smm_relocate(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 448 | } |
| 449 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 450 | static void post_mp_init(void) |
| 451 | { |
| 452 | /* Set Max Ratio */ |
| 453 | cpu_set_max_ratio(); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 454 | |
| 455 | /* |
| 456 | * Now that all APs have been relocated as well as the BSP let SMIs |
| 457 | * start flowing. |
| 458 | */ |
Subrata Banik | 47a655c | 2017-12-14 18:22:13 +0530 | [diff] [blame] | 459 | smm_southbridge_enable(PWRBTN_EN | GBL_EN); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 460 | |
| 461 | /* Lock down the SMRAM space. */ |
| 462 | smm_lock(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 463 | } |
| 464 | |
| 465 | static const struct mp_ops mp_ops = { |
| 466 | /* |
| 467 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 468 | * that are set prior to ramstage. |
| 469 | * Real MTRRs programming are being done after resource allocation. |
| 470 | */ |
| 471 | .pre_mp_init = soc_fsp_load, |
| 472 | .get_cpu_count = get_cpu_count, |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 473 | .get_smm_info = smm_info, |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 474 | .get_microcode_info = get_microcode_info, |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 475 | .pre_mp_smm_init = smm_initialize, |
| 476 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 477 | .relocation_handler = smm_relocation_handler, |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 478 | .post_mp_init = post_mp_init, |
| 479 | }; |
| 480 | |
| 481 | void soc_init_cpus(struct bus *cpu_bus) |
| 482 | { |
| 483 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 484 | printk(BIOS_ERR, "MP initialization failure.\n"); |
John Su | 3126964 | 2019-01-10 14:53:26 +0800 | [diff] [blame] | 485 | |
| 486 | /* Thermal throttle activation offset */ |
| 487 | configure_thermal_target(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 488 | } |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 489 | |
| 490 | int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) |
| 491 | { |
| 492 | msr_t msr1; |
| 493 | msr_t msr2; |
| 494 | |
| 495 | /* |
| 496 | * CFL and WHL CPU die are based on KBL CPU so we need to |
| 497 | * have this check, where CNL CPU die is not based on KBL CPU |
| 498 | * so skip this check for CNL. |
| 499 | */ |
| 500 | if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)) |
| 501 | return 0; |
| 502 | |
| 503 | /* |
| 504 | * If PRMRR/SGX is supported the FIT microcode load will set the msr |
| 505 | * 0x08b with the Patch revision id one less than the id in the |
| 506 | * microcode binary. The PRMRR support is indicated in the MSR |
| 507 | * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the |
| 508 | * same microcode during CPU initialization. If SGX is enabled, as |
| 509 | * part of SGX BIOS initialization steps, the same microcode needs to |
| 510 | * be reloaded after the core PRMRR MSRs are programmed. |
| 511 | */ |
| 512 | msr1 = rdmsr(MTRR_CAP_MSR); |
| 513 | msr2 = rdmsr(MSR_PRMRR_PHYS_BASE); |
| 514 | if (msr2.lo && (current_patch_id == new_patch_id - 1)) |
| 515 | return 0; |
| 516 | |
| 517 | return (msr1.lo & PRMRR_SUPPORTED) && |
| 518 | (current_patch_id == new_patch_id - 1); |
| 519 | } |