Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/acpi.h> |
| 18 | #include <arch/acpigen.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 19 | #include <device/mmio.h> |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 20 | #include <arch/smp/mpspec.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 21 | #include <cbmem.h> |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 22 | #include <console/console.h> |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 23 | #include <cpu/x86/smm.h> |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 24 | #include <types.h> |
| 25 | #include <string.h> |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 26 | #include <cpu/x86/msr.h> |
| 27 | #include <cpu/x86/tsc.h> |
| 28 | #include <cpu/intel/turbo.h> |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 29 | |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 30 | #include <soc/acpi.h> |
| 31 | #include <soc/iomap.h> |
| 32 | #include <soc/irq.h> |
| 33 | #include <soc/msr.h> |
| 34 | #include <soc/pattrs.h> |
| 35 | #include <soc/pmc.h> |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 36 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 37 | #include <ec/google/chromeec/ec.h> |
| 38 | #include <vendorcode/google/chromeos/gnvs.h> |
| 39 | |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 40 | #define MWAIT_RES(state, sub_state) \ |
| 41 | { \ |
| 42 | .addrl = (((state) << 4) | (sub_state)), \ |
| 43 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 44 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 45 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 46 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 47 | } |
| 48 | |
| 49 | /* C-state map without S0ix */ |
| 50 | static acpi_cstate_t cstate_map[] = { |
| 51 | { |
| 52 | /* C1 */ |
| 53 | .ctype = 1, /* ACPI C1 */ |
| 54 | .latency = 1, |
| 55 | .power = 1000, |
| 56 | .resource = MWAIT_RES(0, 0), |
| 57 | }, |
| 58 | { |
| 59 | /* C6NS with no L2 shrink */ |
| 60 | /* NOTE: this substate is above CPUID limit */ |
| 61 | .ctype = 2, /* ACPI C2 */ |
| 62 | .latency = 500, |
| 63 | .power = 10, |
Duncan Laurie | 22f1dcd | 2013-12-02 10:14:47 -0800 | [diff] [blame] | 64 | .resource = MWAIT_RES(5, 1), |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 65 | }, |
| 66 | { |
| 67 | /* C6FS with full L2 shrink */ |
| 68 | .ctype = 3, /* ACPI C3 */ |
| 69 | .latency = 1500, /* 1.5ms worst case */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 70 | .power = 1, |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 71 | .resource = MWAIT_RES(5, 2), |
| 72 | } |
| 73 | }; |
| 74 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 75 | void acpi_init_gnvs(global_nvs_t *gnvs) |
| 76 | { |
| 77 | /* Set unknown wake source */ |
| 78 | gnvs->pm1i = -1; |
| 79 | |
| 80 | /* CPU core count */ |
| 81 | gnvs->pcnt = dev_count_cpu(); |
| 82 | |
| 83 | /* Top of Low Memory (start of resource allocation) */ |
| 84 | gnvs->tolm = nc_read_top_of_low_memory(); |
| 85 | |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 86 | #if IS_ENABLED(CONFIG_CONSOLE_CBMEM) |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 87 | /* Update the mem console pointer. */ |
| 88 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 89 | #endif |
| 90 | |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 91 | #if IS_ENABLED(CONFIG_CHROMEOS) |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 92 | /* Initialize Verified Boot data */ |
Joel Kitching | 6fbd874 | 2018-08-23 14:56:25 +0800 | [diff] [blame] | 93 | chromeos_init_chromeos_acpi(&(gnvs->chromeos)); |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 94 | #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 95 | gnvs->chromeos.vbt2 = google_ec_running_ro() ? |
| 96 | ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; |
| 97 | #endif |
| 98 | #endif |
| 99 | } |
| 100 | |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 101 | static int acpi_sci_irq(void) |
| 102 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 103 | u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 104 | int scis; |
| 105 | static int sci_irq; |
| 106 | |
| 107 | if (sci_irq) |
| 108 | return sci_irq; |
| 109 | |
| 110 | /* Determine how SCI is routed. */ |
| 111 | scis = read32(actl) & SCIS_MASK; |
| 112 | switch (scis) { |
| 113 | case SCIS_IRQ9: |
| 114 | case SCIS_IRQ10: |
| 115 | case SCIS_IRQ11: |
| 116 | sci_irq = scis - SCIS_IRQ9 + 9; |
| 117 | break; |
| 118 | case SCIS_IRQ20: |
| 119 | case SCIS_IRQ21: |
| 120 | case SCIS_IRQ22: |
| 121 | case SCIS_IRQ23: |
| 122 | sci_irq = scis - SCIS_IRQ20 + 20; |
| 123 | break; |
| 124 | default: |
| 125 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); |
| 126 | sci_irq = 9; |
| 127 | break; |
| 128 | } |
| 129 | |
| 130 | printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); |
| 131 | return sci_irq; |
| 132 | } |
| 133 | |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 134 | void acpi_create_intel_hpet(acpi_hpet_t * hpet) |
| 135 | { |
| 136 | acpi_header_t *header = &(hpet->header); |
| 137 | acpi_addr_t *addr = &(hpet->addr); |
| 138 | |
| 139 | memset((void *) hpet, 0, sizeof(acpi_hpet_t)); |
| 140 | |
| 141 | /* fill out header fields */ |
| 142 | memcpy(header->signature, "HPET", 4); |
| 143 | memcpy(header->oem_id, OEM_ID, 6); |
| 144 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 145 | memcpy(header->asl_compiler_id, ASLC, 4); |
| 146 | |
| 147 | header->length = sizeof(acpi_hpet_t); |
Marc Jones | 8abf6ae | 2018-08-22 19:08:52 -0600 | [diff] [blame] | 148 | header->revision = get_acpi_table_revision(HPET); |
Aaron Durbin | 61cd57b | 2013-10-30 14:36:11 -0500 | [diff] [blame] | 149 | |
| 150 | /* fill out HPET address */ |
| 151 | addr->space_id = 0; /* Memory */ |
| 152 | addr->bit_width = 64; |
| 153 | addr->bit_offset = 0; |
| 154 | addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; |
| 155 | addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; |
| 156 | |
| 157 | hpet->id = 0x8086a201; /* Intel */ |
| 158 | hpet->number = 0x00; |
| 159 | hpet->min_tick = 0x0080; |
| 160 | |
| 161 | header->checksum = |
| 162 | acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); |
| 163 | } |
Duncan Laurie | 03ff2a2 | 2013-11-04 17:15:20 -0800 | [diff] [blame] | 164 | |
| 165 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 166 | { |
| 167 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 168 | MCFG_BASE_ADDRESS, 0, 0, 255); |
| 169 | return current; |
| 170 | } |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 171 | |
| 172 | void acpi_fill_in_fadt(acpi_fadt_t *fadt) |
| 173 | { |
| 174 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 175 | |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 176 | fadt->sci_int = acpi_sci_irq(); |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 177 | fadt->smi_cmd = APM_CNT; |
| 178 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 179 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 180 | fadt->s4bios_req = 0x0; |
| 181 | fadt->pstate_cnt = 0; |
| 182 | |
| 183 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 184 | fadt->pm1b_evt_blk = 0x0; |
| 185 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 186 | fadt->pm1b_cnt_blk = 0x0; |
| 187 | fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; |
| 188 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 189 | fadt->gpe0_blk = pmbase + GPE0_STS; |
| 190 | fadt->gpe1_blk = 0; |
| 191 | |
| 192 | fadt->pm1_evt_len = 4; |
| 193 | fadt->pm1_cnt_len = 2; |
| 194 | fadt->pm2_cnt_len = 1; |
| 195 | fadt->pm_tmr_len = 4; |
Aaron Durbin | 997d252 | 2013-11-08 17:37:48 -0600 | [diff] [blame] | 196 | fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 197 | fadt->gpe1_blk_len = 0; |
| 198 | fadt->gpe1_base = 0; |
| 199 | fadt->cst_cnt = 0; |
| 200 | fadt->p_lvl2_lat = 1; |
| 201 | fadt->p_lvl3_lat = 87; |
| 202 | fadt->flush_size = 1024; |
| 203 | fadt->flush_stride = 16; |
| 204 | fadt->duty_offset = 1; |
| 205 | fadt->duty_width = 0; |
| 206 | fadt->day_alrm = 0xd; |
| 207 | fadt->mon_alrm = 0x00; |
| 208 | fadt->century = 0x00; |
| 209 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 210 | |
| 211 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 212 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 213 | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | |
| 214 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 215 | |
| 216 | fadt->reset_reg.space_id = 1; |
| 217 | fadt->reset_reg.bit_width = 8; |
| 218 | fadt->reset_reg.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 219 | fadt->reset_reg.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 220 | fadt->reset_reg.addrl = 0xcf9; |
| 221 | fadt->reset_reg.addrh = 0; |
| 222 | fadt->reset_value = 6; |
| 223 | |
| 224 | fadt->x_pm1a_evt_blk.space_id = 1; |
Aaron Durbin | 997d252 | 2013-11-08 17:37:48 -0600 | [diff] [blame] | 225 | fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 226 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 227 | fadt->x_pm1a_evt_blk.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 228 | fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
| 229 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 230 | |
| 231 | fadt->x_pm1b_evt_blk.space_id = 1; |
| 232 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 233 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 234 | fadt->x_pm1b_evt_blk.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 235 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 236 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 237 | |
| 238 | fadt->x_pm1a_cnt_blk.space_id = 1; |
Aaron Durbin | 997d252 | 2013-11-08 17:37:48 -0600 | [diff] [blame] | 239 | fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 240 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 241 | fadt->x_pm1a_cnt_blk.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 242 | fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
| 243 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 244 | |
| 245 | fadt->x_pm1b_cnt_blk.space_id = 1; |
| 246 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 247 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 248 | fadt->x_pm1b_cnt_blk.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 249 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 250 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 251 | |
| 252 | fadt->x_pm2_cnt_blk.space_id = 1; |
Aaron Durbin | 997d252 | 2013-11-08 17:37:48 -0600 | [diff] [blame] | 253 | fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 254 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 255 | fadt->x_pm2_cnt_blk.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 256 | fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; |
| 257 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 258 | |
| 259 | fadt->x_pm_tmr_blk.space_id = 1; |
Aaron Durbin | 997d252 | 2013-11-08 17:37:48 -0600 | [diff] [blame] | 260 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 261 | fadt->x_pm_tmr_blk.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 262 | fadt->x_pm_tmr_blk.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 263 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 264 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 265 | |
| 266 | fadt->x_gpe0_blk.space_id = 1; |
Aaron Durbin | 997d252 | 2013-11-08 17:37:48 -0600 | [diff] [blame] | 267 | fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 268 | fadt->x_gpe0_blk.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 269 | fadt->x_gpe0_blk.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 270 | fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; |
| 271 | fadt->x_gpe0_blk.addrh = 0x0; |
| 272 | |
| 273 | fadt->x_gpe1_blk.space_id = 1; |
| 274 | fadt->x_gpe1_blk.bit_width = 0; |
| 275 | fadt->x_gpe1_blk.bit_offset = 0; |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 276 | fadt->x_gpe1_blk.access_size = 0; |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 277 | fadt->x_gpe1_blk.addrl = 0x0; |
| 278 | fadt->x_gpe1_blk.addrh = 0x0; |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 279 | } |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 280 | |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 281 | static acpi_tstate_t baytrail_tss_table[] = { |
| 282 | { 100, 1000, 0, 0x00, 0 }, |
| 283 | { 88, 875, 0, 0x1e, 0 }, |
| 284 | { 75, 750, 0, 0x1c, 0 }, |
| 285 | { 63, 625, 0, 0x1a, 0 }, |
| 286 | { 50, 500, 0, 0x18, 0 }, |
| 287 | { 38, 375, 0, 0x16, 0 }, |
| 288 | { 25, 250, 0, 0x14, 0 }, |
| 289 | { 13, 125, 0, 0x12, 0 }, |
| 290 | }; |
| 291 | |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 292 | static void generate_T_state_entries(int core, int cores_per_package) |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 293 | { |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 294 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 295 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 296 | |
| 297 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 298 | acpigen_write_empty_PTC(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 299 | |
| 300 | /* Set NVS controlled T-state limit */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 301 | acpigen_write_TPC("\\TLVL"); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 302 | |
| 303 | /* Write TSS table for MSR access */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 304 | acpigen_write_TSS_package( |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 305 | ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 309 | { |
| 310 | u32 m; |
| 311 | u32 power; |
| 312 | |
| 313 | /* |
| 314 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 315 | * |
| 316 | * Power = (ratio / p1_ratio) * m * tdp |
| 317 | */ |
| 318 | |
| 319 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 320 | m = (m * m) / 1000; |
| 321 | |
| 322 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 323 | power *= (m / 100) * (tdp / 1000); |
| 324 | power /= 1000; |
| 325 | |
| 326 | return (int)power; |
| 327 | } |
| 328 | |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 329 | static void generate_P_state_entries(int core, int cores_per_package) |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 330 | { |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 331 | int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; |
| 332 | int coord_type, power_max, power_unit, num_entries; |
| 333 | int ratio, power, clock, clock_max; |
| 334 | int vid, vid_turbo, vid_min, vid_max, vid_range_2; |
| 335 | u32 control_status; |
| 336 | const struct pattrs *pattrs = pattrs_get(); |
| 337 | msr_t msr; |
| 338 | |
| 339 | /* Inputs from CPU attributes */ |
| 340 | ratio_max = pattrs->iacore_ratios[IACORE_MAX]; |
| 341 | ratio_min = pattrs->iacore_ratios[IACORE_LFM]; |
| 342 | vid_max = pattrs->iacore_vids[IACORE_MAX]; |
| 343 | vid_min = pattrs->iacore_vids[IACORE_LFM]; |
| 344 | |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 345 | /* Set P-states coordination type based on MSR disable bit */ |
Duncan Laurie | 31ac9e3 | 2014-03-28 10:52:13 -0700 | [diff] [blame] | 346 | coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL; |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 347 | |
| 348 | /* Max Non-Turbo Frequency */ |
| 349 | clock_max = (ratio_max * pattrs->bclk_khz) / 1000; |
| 350 | |
| 351 | /* Calculate CPU TDP in mW */ |
| 352 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 353 | power_unit = 1 << (msr.lo & 0xf); |
| 354 | msr = rdmsr(MSR_PKG_POWER_LIMIT); |
| 355 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 356 | |
| 357 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 358 | acpigen_write_empty_PCT(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 359 | |
Duncan Laurie | ad8d913 | 2013-12-10 07:41:33 -0800 | [diff] [blame] | 360 | /* Write _PPC with NVS specified limit on supported P-state */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 361 | acpigen_write_PPC_NVS(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 362 | |
| 363 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 364 | acpigen_write_PSD_package(core, 1, coord_type); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 365 | |
| 366 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 367 | acpigen_write_name("_PSS"); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 368 | |
| 369 | /* Determine ratio points */ |
| 370 | ratio_step = 1; |
| 371 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 372 | while (num_entries > 15) { /* ACPI max is 15 ratios */ |
| 373 | ratio_step <<= 1; |
| 374 | num_entries >>= 1; |
| 375 | } |
| 376 | |
| 377 | /* P[T] is Turbo state if enabled */ |
| 378 | if (get_turbo_state() == TURBO_ENABLED) { |
| 379 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 380 | acpigen_write_package(num_entries + 2); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 381 | |
| 382 | ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; |
| 383 | vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; |
| 384 | control_status = (ratio_turbo << 8) | vid_turbo; |
| 385 | |
| 386 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 387 | acpigen_write_PSS_package( |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 388 | clock_max + 1, /*MHz*/ |
| 389 | power_max, /*mW*/ |
| 390 | 10, /*lat1*/ |
| 391 | 10, /*lat2*/ |
| 392 | control_status, /*control*/ |
| 393 | control_status); /*status*/ |
| 394 | } else { |
| 395 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 396 | acpigen_write_package(num_entries + 1); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 397 | ratio_turbo = ratio_max; |
| 398 | vid_turbo = vid_max; |
| 399 | } |
| 400 | |
| 401 | /* First regular entry is max non-turbo ratio */ |
| 402 | control_status = (ratio_max << 8) | vid_max; |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 403 | acpigen_write_PSS_package( |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 404 | clock_max, /*MHz*/ |
| 405 | power_max, /*mW*/ |
| 406 | 10, /*lat1*/ |
| 407 | 10, /*lat2*/ |
| 408 | control_status, /*control */ |
| 409 | control_status); /*status*/ |
| 410 | |
| 411 | /* Set up ratio and vid ranges for VID calculation */ |
| 412 | ratio_range_2 = (ratio_turbo - ratio_min) * 2; |
| 413 | vid_range_2 = (vid_turbo - vid_min) * 2; |
| 414 | |
| 415 | /* Generate the remaining entries */ |
| 416 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 417 | ratio >= ratio_min; ratio -= ratio_step) { |
| 418 | |
| 419 | /* Calculate VID for this ratio */ |
| 420 | vid = ((ratio - ratio_min) * vid_range_2) / |
| 421 | ratio_range_2 + vid_min; |
| 422 | /* Round up if remainder */ |
| 423 | if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) |
| 424 | vid++; |
| 425 | |
| 426 | /* Calculate power at this ratio */ |
| 427 | power = calculate_power(power_max, ratio_max, ratio); |
| 428 | clock = (ratio * pattrs->bclk_khz) / 1000; |
| 429 | control_status = (ratio << 8) | (vid & 0xff); |
| 430 | |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 431 | acpigen_write_PSS_package( |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 432 | clock, /*MHz*/ |
| 433 | power, /*mW*/ |
| 434 | 10, /*lat1*/ |
| 435 | 10, /*lat2*/ |
| 436 | control_status, /*control*/ |
| 437 | control_status); /*status*/ |
| 438 | } |
| 439 | |
| 440 | /* Fix package length */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 441 | acpigen_pop_len(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 442 | } |
| 443 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 444 | void generate_cpu_entries(struct device *device) |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 445 | { |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 446 | int core; |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 447 | int pcontrol_blk = get_pmbase(), plen = 6; |
| 448 | const struct pattrs *pattrs = pattrs_get(); |
| 449 | |
Arthur Heymans | a783305 | 2018-11-28 12:20:14 +0100 | [diff] [blame] | 450 | for (core = 0; core < pattrs->num_cpus; core++) { |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 451 | if (core > 0) { |
| 452 | pcontrol_blk = 0; |
| 453 | plen = 0; |
| 454 | } |
| 455 | |
| 456 | /* Generate processor \_PR.CPUx */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 457 | acpigen_write_processor( |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 458 | core, pcontrol_blk, plen); |
| 459 | |
| 460 | /* Generate P-state tables */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 461 | generate_P_state_entries( |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 462 | core, pattrs->num_cpus); |
| 463 | |
| 464 | /* Generate C-state tables */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 465 | acpigen_write_CST_package( |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 466 | cstate_map, ARRAY_SIZE(cstate_map)); |
| 467 | |
| 468 | /* Generate T-state tables */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 469 | generate_T_state_entries( |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 470 | core, pattrs->num_cpus); |
| 471 | |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 472 | acpigen_pop_len(); |
Duncan Laurie | 8923be5 | 2013-11-05 13:02:30 -0800 | [diff] [blame] | 473 | } |
Arthur Heymans | a783305 | 2018-11-28 12:20:14 +0100 | [diff] [blame] | 474 | |
| 475 | /* PPKG is usually used for thermal management |
| 476 | of the first and only package. */ |
| 477 | acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus); |
| 478 | |
| 479 | /* Add a method to notify processor nodes */ |
| 480 | acpigen_write_processor_cnot(pattrs->num_cpus); |
Aaron Durbin | 303525b | 2013-11-05 11:42:32 -0600 | [diff] [blame] | 481 | } |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 482 | |
| 483 | unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 484 | { |
| 485 | int sci_irq = acpi_sci_irq(); |
| 486 | acpi_madt_irqoverride_t *irqovr; |
| 487 | uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; |
| 488 | |
| 489 | /* INT_SRC_OVR */ |
| 490 | irqovr = (void *)current; |
| 491 | current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); |
| 492 | |
| 493 | if (sci_irq >= 20) |
| 494 | sci_flags |= MP_IRQ_POLARITY_LOW; |
| 495 | else |
| 496 | sci_flags |= MP_IRQ_POLARITY_HIGH; |
| 497 | |
| 498 | irqovr = (void *)current; |
| 499 | current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, |
| 500 | sci_flags); |
| 501 | |
| 502 | return current; |
| 503 | } |