Andrey Petrov | 491c016 | 2016-03-02 15:09:27 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Andrey Petrov | 491c016 | 2016-03-02 15:09:27 -0800 | [diff] [blame] | 16 | */ |
| 17 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 18 | #include <assert.h> |
Andrey Petrov | 491c016 | 2016-03-02 15:09:27 -0800 | [diff] [blame] | 19 | #include <cbmem.h> |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 20 | #include "chip.h" |
Andrey Petrov | 491c016 | 2016-03-02 15:09:27 -0800 | [diff] [blame] | 21 | #include <device/pci.h> |
Brandon Breitenstein | a86d1b8 | 2017-06-08 17:32:02 -0700 | [diff] [blame] | 22 | #include <fsp/memmap.h> |
Subrata Banik | ce90c78 | 2017-08-30 16:53:20 +0530 | [diff] [blame] | 23 | #include <intelblocks/smm.h> |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 24 | #include <soc/systemagent.h> |
Andrey Petrov | 491c016 | 2016-03-02 15:09:27 -0800 | [diff] [blame] | 25 | #include <soc/pci_devs.h> |
| 26 | |
Andrey Petrov | 491c016 | 2016-03-02 15:09:27 -0800 | [diff] [blame] | 27 | void *cbmem_top(void) |
| 28 | { |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 29 | const struct device *dev; |
| 30 | const config_t *config; |
| 31 | void *tolum = (void *)sa_get_tseg_base(); |
| 32 | |
| 33 | if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) |
| 34 | return tolum; |
| 35 | |
| 36 | dev = dev_find_slot(0, PCH_DEVFN_LPC); |
| 37 | assert(dev != NULL); |
| 38 | config = dev->chip_info; |
| 39 | |
| 40 | if (!config) |
| 41 | die("Failed to get chip_info\n"); |
| 42 | |
| 43 | /* FSP allocates 2x PRMRR Size Memory for alignment */ |
| 44 | if (config->sgx_enable) |
| 45 | tolum -= config->PrmrrSize * 2; |
| 46 | |
| 47 | return tolum; |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 48 | } |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 49 | |
| 50 | int smm_subregion(int sub, void **start, size_t *size) |
| 51 | { |
| 52 | uintptr_t sub_base; |
| 53 | size_t sub_size; |
Subrata Banik | ce90c78 | 2017-08-30 16:53:20 +0530 | [diff] [blame] | 54 | void *smm_base; |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 55 | const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; |
| 56 | |
Subrata Banik | ce90c78 | 2017-08-30 16:53:20 +0530 | [diff] [blame] | 57 | smm_region_info(&smm_base, &sub_size); |
| 58 | sub_base = (uintptr_t)smm_base; |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 59 | |
| 60 | assert(sub_size > CONFIG_SMM_RESERVED_SIZE); |
| 61 | |
| 62 | switch (sub) { |
| 63 | case SMM_SUBREGION_HANDLER: |
| 64 | /* Handler starts at the base of TSEG. */ |
| 65 | sub_size -= cache_size; |
| 66 | break; |
| 67 | case SMM_SUBREGION_CACHE: |
| 68 | /* External cache is in the middle of TSEG. */ |
| 69 | sub_base += sub_size - cache_size; |
| 70 | sub_size = cache_size; |
| 71 | break; |
| 72 | default: |
| 73 | return -1; |
| 74 | } |
| 75 | |
| 76 | *start = (void *)sub_base; |
| 77 | *size = sub_size; |
| 78 | |
| 79 | return 0; |
| 80 | } |