Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 4 | * Copyright (C) 2015-2017 Intel Corp. |
Mario Scheithauer | d0e5133 | 2017-10-24 16:57:26 +0200 | [diff] [blame] | 5 | * Copyright (C) 2017 Siemens AG, Inc. |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 18 | */ |
| 19 | |
Nico Huber | aa4d9b9 | 2019-02-01 14:20:37 +0100 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 21 | #include <assert.h> |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 22 | #include <console/console.h> |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 23 | #include "chip.h" |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 24 | #include <cpu/cpu.h> |
| 25 | #include <cpu/x86/cache.h> |
| 26 | #include <cpu/x86/mp.h> |
John Zhao | 3156934 | 2016-08-23 16:38:05 -0700 | [diff] [blame] | 27 | #include <cpu/intel/microcode.h> |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 28 | #include <cpu/intel/turbo.h> |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 29 | #include <cpu/x86/msr.h> |
| 30 | #include <cpu/x86/mtrr.h> |
| 31 | #include <device/device.h> |
| 32 | #include <device/pci.h> |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 33 | #include <fsp/api.h> |
Brandon Breitenstein | a86d1b8 | 2017-06-08 17:32:02 -0700 | [diff] [blame] | 34 | #include <fsp/memmap.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 35 | #include <intelblocks/cpulib.h> |
Aaron Durbin | efc92a8 | 2017-06-08 10:54:59 -0500 | [diff] [blame] | 36 | #include <intelblocks/fast_spi.h> |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 37 | #include <intelblocks/mp_init.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 38 | #include <intelblocks/msr.h> |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 39 | #include <intelblocks/sgx.h> |
Brandon Breitenstein | a86d1b8 | 2017-06-08 17:32:02 -0700 | [diff] [blame] | 40 | #include <intelblocks/smm.h> |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 41 | #include <reg_script.h> |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 42 | #include <romstage_handoff.h> |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 43 | #include <soc/cpu.h> |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 44 | #include <soc/iomap.h> |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 45 | #include <soc/pci_devs.h> |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 46 | #include <soc/pm.h> |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 47 | |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 48 | static const struct reg_script core_msr_script[] = { |
Cole Nelson | f357c25 | 2017-05-16 11:38:59 -0700 | [diff] [blame] | 49 | #if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 50 | /* Enable C-state and IO/MWAIT redirect */ |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 51 | REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL, |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 52 | (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK |
| 53 | | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), |
| 54 | /* Power Management I/O base address for I/O trapping to C-states */ |
| 55 | REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, |
| 56 | (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), |
Venkateswarlu Vinjamuri | 362180a | 2016-10-31 17:03:55 -0700 | [diff] [blame] | 57 | /* Disable support for MONITOR and MWAIT instructions */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 58 | REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0), |
Cole Nelson | f357c25 | 2017-05-16 11:38:59 -0700 | [diff] [blame] | 59 | #endif |
Cole Nelson | 9d0950f | 2018-06-12 10:02:49 -0700 | [diff] [blame] | 60 | /* Disable C1E */ |
| 61 | REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), |
Nelson, Cole | 1cf5b87 | 2016-11-11 14:17:37 -0800 | [diff] [blame] | 62 | /* |
| 63 | * Enable and Lock the Advanced Encryption Standard (AES-NI) |
| 64 | * feature register |
| 65 | */ |
| 66 | REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, |
| 67 | FEATURE_CONFIG_LOCK), |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 68 | REG_SCRIPT_END |
| 69 | }; |
| 70 | |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 71 | void soc_core_init(struct device *cpu) |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 72 | { |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 73 | /* Clear out pending MCEs */ |
Nico Huber | aa4d9b9 | 2019-02-01 14:20:37 +0100 | [diff] [blame] | 74 | /* TODO(adurbin): Some of these banks are core vs package |
| 75 | scope. For now every CPU clears every bank. */ |
Julius Werner | 175aa69 | 2019-03-04 18:21:50 -0800 | [diff] [blame] | 76 | if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) || |
Nico Huber | aa4d9b9 | 2019-02-01 14:20:37 +0100 | [diff] [blame] | 77 | acpi_get_sleep_type() == ACPI_S5) |
| 78 | mca_configure(NULL); |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 79 | |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 80 | /* Set core MSRs */ |
| 81 | reg_script_run(core_msr_script); |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 82 | /* |
| 83 | * Enable ACPI PM timer emulation, which also lets microcode know |
Barnali Sarkar | 9e55ff6 | 2017-06-05 20:01:14 +0530 | [diff] [blame] | 84 | * location of ACPI_BASE_ADDRESS. This also enables other features |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 85 | * implemented in microcode. |
| 86 | */ |
| 87 | enable_pm_timer_emulation(); |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 88 | |
| 89 | /* Configure Core PRMRR for SGX. */ |
| 90 | if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) |
| 91 | prmrr_core_configure(); |
Mario Scheithauer | d0e5133 | 2017-10-24 16:57:26 +0200 | [diff] [blame] | 92 | |
| 93 | /* Set Max Non-Turbo ratio if RAPL is disabled. */ |
| 94 | if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) { |
| 95 | cpu_set_p_state_to_max_non_turbo_ratio(); |
| 96 | cpu_disable_eist(); |
Werner Zeh | 2636186 | 2018-11-21 12:36:21 +0100 | [diff] [blame] | 97 | } else if (IS_ENABLED(CONFIG_APL_SET_MIN_CLOCK_RATIO)) { |
| 98 | cpu_set_p_state_to_min_clock_ratio(); |
| 99 | cpu_disable_eist(); |
Mario Scheithauer | d0e5133 | 2017-10-24 16:57:26 +0200 | [diff] [blame] | 100 | } |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 101 | } |
| 102 | |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 103 | #if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 104 | static void soc_init_core(struct device *cpu) |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 105 | { |
Pratik Prajapati | 9cd6a26 | 2017-08-14 13:57:46 -0700 | [diff] [blame] | 106 | soc_core_init(cpu); |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 107 | } |
| 108 | |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 109 | static struct device_operations cpu_dev_ops = { |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 110 | .init = soc_init_core, |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 111 | }; |
| 112 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 113 | static const struct cpu_device_id cpu_table[] = { |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 114 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, |
| 115 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 }, |
Mario Scheithauer | 545593d | 2017-10-24 17:41:19 +0200 | [diff] [blame] | 116 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 117 | { X86_VENDOR_INTEL, CPUID_GLK_A0 }, |
| 118 | { X86_VENDOR_INTEL, CPUID_GLK_B0 }, |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 119 | { 0, 0 }, |
| 120 | }; |
| 121 | |
| 122 | static const struct cpu_driver driver __cpu_driver = { |
| 123 | .ops = &cpu_dev_ops, |
| 124 | .id_table = cpu_table, |
| 125 | }; |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 126 | #endif |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 127 | |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 128 | /* |
| 129 | * MP and SMM loading initialization. |
| 130 | */ |
| 131 | struct smm_relocation_attrs { |
| 132 | uint32_t smbase; |
| 133 | uint32_t smrr_base; |
| 134 | uint32_t smrr_mask; |
| 135 | }; |
| 136 | |
| 137 | static struct smm_relocation_attrs relo_attrs; |
| 138 | |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 139 | /* |
| 140 | * Do essential initialization tasks before APs can be fired up. |
| 141 | * |
| 142 | * IF (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) - |
| 143 | * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP, |
| 144 | * that are set prior to ramstage. |
| 145 | * Real MTRRs are programmed after resource allocation. |
| 146 | * |
| 147 | * Do FSP loading before MP Init to ensure that the FSP component stored in |
| 148 | * external stage cache in TSEG does not flush off due to SMM relocation |
| 149 | * during MP Init stage. |
| 150 | * |
| 151 | * ELSE - |
| 152 | * Enable MTRRs on the BSP. This creates the MTRR solution that the |
| 153 | * APs will use. Otherwise APs will try to apply the incomplete solution |
| 154 | * as the BSP is calculating it. |
| 155 | */ |
| 156 | static void pre_mp_init(void) |
| 157 | { |
| 158 | if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) { |
| 159 | fsps_load(romstage_handoff_is_resume()); |
| 160 | return; |
| 161 | } |
| 162 | x86_setup_mtrrs_with_detect(); |
| 163 | x86_mtrr_check(); |
| 164 | } |
| 165 | |
| 166 | #if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 167 | static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) |
| 168 | { |
| 169 | msr_t msr; |
| 170 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
| 171 | *num_virt = (msr.lo >> 0) & 0xffff; |
| 172 | *num_phys = (msr.lo >> 16) & 0xffff; |
| 173 | } |
| 174 | |
Aaron Durbin | e72b9d4 | 2016-05-03 15:56:24 -0500 | [diff] [blame] | 175 | /* Find CPU topology */ |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 176 | int get_cpu_count(void) |
Aaron Durbin | e72b9d4 | 2016-05-03 15:56:24 -0500 | [diff] [blame] | 177 | { |
| 178 | unsigned int num_virt_cores, num_phys_cores; |
| 179 | |
| 180 | read_cpu_topology(&num_phys_cores, &num_virt_cores); |
| 181 | |
| 182 | printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n", |
| 183 | num_phys_cores, num_virt_cores); |
| 184 | |
| 185 | return num_virt_cores; |
| 186 | } |
| 187 | |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 188 | void get_microcode_info(const void **microcode, int *parallel) |
John Zhao | 3156934 | 2016-08-23 16:38:05 -0700 | [diff] [blame] | 189 | { |
| 190 | *microcode = intel_microcode_find(); |
| 191 | *parallel = 1; |
Barnali Sarkar | 97daf98 | 2017-06-07 13:47:51 +0530 | [diff] [blame] | 192 | |
| 193 | /* Make sure BSP is using the microcode from cbfs */ |
| 194 | intel_microcode_load_unlocked(*microcode); |
John Zhao | 3156934 | 2016-08-23 16:38:05 -0700 | [diff] [blame] | 195 | } |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 196 | #endif |
John Zhao | 3156934 | 2016-08-23 16:38:05 -0700 | [diff] [blame] | 197 | |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 198 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 199 | size_t *smm_save_state_size) |
| 200 | { |
| 201 | void *smm_base; |
| 202 | size_t smm_size; |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 203 | void *handler_base; |
| 204 | size_t handler_size; |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 205 | |
| 206 | /* All range registers are aligned to 4KiB */ |
| 207 | const uint32_t rmask = ~((1 << 12) - 1); |
| 208 | |
| 209 | /* Initialize global tracking state. */ |
Subrata Banik | ce90c78 | 2017-08-30 16:53:20 +0530 | [diff] [blame] | 210 | smm_region_info(&smm_base, &smm_size); |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 211 | smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); |
| 212 | |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 213 | relo_attrs.smbase = (uint32_t)smm_base; |
| 214 | relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; |
| 215 | relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; |
| 216 | relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; |
| 217 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 218 | *perm_smbase = (uintptr_t)handler_base; |
| 219 | *perm_smsize = handler_size; |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 220 | *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); |
| 221 | } |
| 222 | |
| 223 | static void relocation_handler(int cpu, uintptr_t curr_smbase, |
| 224 | uintptr_t staggered_smbase) |
| 225 | { |
| 226 | msr_t smrr; |
| 227 | em64t100_smm_state_save_area_t *smm_state; |
| 228 | /* Set up SMRR. */ |
| 229 | smrr.lo = relo_attrs.smrr_base; |
| 230 | smrr.hi = 0; |
Arthur Heymans | e750b38e | 2018-07-20 23:31:59 +0200 | [diff] [blame] | 231 | wrmsr(IA32_SMRR_PHYS_BASE, smrr); |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 232 | smrr.lo = relo_attrs.smrr_mask; |
| 233 | smrr.hi = 0; |
Arthur Heymans | e750b38e | 2018-07-20 23:31:59 +0200 | [diff] [blame] | 234 | wrmsr(IA32_SMRR_PHYS_MASK, smrr); |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 235 | smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); |
| 236 | smm_state->smbase = staggered_smbase; |
| 237 | } |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 238 | /* |
| 239 | * CPU initialization recipe |
| 240 | * |
| 241 | * Note that no microcode update is passed to the init function. CSE updates |
| 242 | * the microcode on all cores before releasing them from reset. That means that |
| 243 | * the BSP and all APs will come up with the same microcode revision. |
| 244 | */ |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 245 | |
| 246 | static void post_mp_init(void) |
| 247 | { |
Subrata Banik | 47a655c | 2017-12-14 18:22:13 +0530 | [diff] [blame] | 248 | smm_southbridge_enable(PWRBTN_EN | GBL_EN); |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 249 | |
| 250 | if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) |
Subrata Banik | 3337497 | 2018-04-24 13:45:30 +0530 | [diff] [blame] | 251 | mp_run_on_all_cpus(sgx_configure, NULL, 2000); |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 252 | } |
| 253 | |
Aaron Durbin | e72b9d4 | 2016-05-03 15:56:24 -0500 | [diff] [blame] | 254 | static const struct mp_ops mp_ops = { |
| 255 | .pre_mp_init = pre_mp_init, |
| 256 | .get_cpu_count = get_cpu_count, |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 257 | .get_smm_info = get_smm_info, |
John Zhao | 3156934 | 2016-08-23 16:38:05 -0700 | [diff] [blame] | 258 | .get_microcode_info = get_microcode_info, |
Brandon Breitenstein | a86d1b8 | 2017-06-08 17:32:02 -0700 | [diff] [blame] | 259 | .pre_mp_smm_init = smm_southbridge_clear_state, |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 260 | .relocation_handler = relocation_handler, |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 261 | .post_mp_init = post_mp_init, |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 262 | }; |
| 263 | |
Pratik Prajapati | 9cd6a26 | 2017-08-14 13:57:46 -0700 | [diff] [blame] | 264 | void soc_init_cpus(struct bus *cpu_bus) |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 265 | { |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 266 | /* Clear for take-off */ |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 267 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 268 | printk(BIOS_ERR, "MP initialization failure.\n"); |
Barnali Sarkar | 1e6b980 | 2017-08-07 18:26:31 +0530 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | void apollolake_init_cpus(struct device *dev) |
| 272 | { |
| 273 | if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) |
| 274 | return; |
Pratik Prajapati | 9cd6a26 | 2017-08-14 13:57:46 -0700 | [diff] [blame] | 275 | soc_init_cpus(dev->link_list); |
Aaron Durbin | bf696f5 | 2016-11-10 20:04:19 -0600 | [diff] [blame] | 276 | |
| 277 | /* Temporarily cache the memory-mapped boot media. */ |
Aaron Durbin | efc92a8 | 2017-06-08 10:54:59 -0500 | [diff] [blame] | 278 | if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && |
| 279 | IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) |
| 280 | fast_spi_cache_bios_region(); |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 281 | } |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 282 | |
| 283 | void cpu_lock_sgx_memory(void) |
| 284 | { |
| 285 | /* Do nothing because MCHECK while loading microcode and enabling |
| 286 | * IA untrusted mode takes care of necessary locking */ |
| 287 | } |
| 288 | |
| 289 | int soc_fill_sgx_param(struct sgx_param *sgx_param) |
| 290 | { |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 291 | struct device *dev = SA_DEV_ROOT; |
Pratik Prajapati | dc194e2 | 2017-08-29 14:27:07 -0700 | [diff] [blame] | 292 | assert(dev != NULL); |
| 293 | config_t *conf = dev->chip_info; |
| 294 | |
| 295 | if (!conf) { |
| 296 | printk(BIOS_ERR, "Failed to get chip_info for SGX param\n"); |
| 297 | return -1; |
| 298 | } |
| 299 | |
| 300 | sgx_param->enable = conf->sgx_enable; |
| 301 | return 0; |
| 302 | } |