Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 4 | * Copyright (C) 2011, 2017 Advanced Micro Devices, Inc. |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC |
| 6 | * Copyright (C) 2017 Google Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 18 | #include <device/device.h> |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 19 | #include <device/pci_def.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 20 | #include <amdblocks/BiosCallOuts.h> |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 21 | #include <soc/southbridge.h> |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 22 | #include <soc/pci_devs.h> |
| 23 | #include <stdlib.h> |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 24 | |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 25 | #include <amdblocks/agesawrapper.h> |
Marc Jones | afd03d8 | 2017-11-16 10:01:08 -0700 | [diff] [blame] | 26 | #include <amdblocks/dimm_spd.h> |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 27 | #include "chip.h" |
Richard Spiegel | a9f4936 | 2018-03-05 08:11:50 -0700 | [diff] [blame] | 28 | #include <amdblocks/car.h> |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 29 | |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 30 | void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {} |
Richard Spiegel | d1a44a1 | 2017-12-26 08:26:31 -0700 | [diff] [blame] | 31 | |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 32 | AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData, |
| 33 | void *ConfigPtr) |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 34 | { |
| 35 | AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; |
| 36 | |
| 37 | if (StdHeader->Func == AMD_INIT_RESET) { |
| 38 | FCH_RESET_DATA_BLOCK *FchParams_reset; |
| 39 | FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; |
| 40 | printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 41 | |
| 42 | /* Get platform specific configuration changes */ |
| 43 | platform_FchParams_reset(FchParams_reset); |
| 44 | |
| 45 | printk(BIOS_DEBUG, "Done\n"); |
| 46 | } |
| 47 | |
| 48 | return AGESA_SUCCESS; |
| 49 | } |
| 50 | |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 51 | AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, |
| 52 | void *ConfigPtr) |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 53 | { |
| 54 | AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 55 | const struct device *dev = pcidev_path_on_root(SATA_DEVFN); |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 56 | |
| 57 | if (StdHeader->Func == AMD_INIT_ENV) { |
| 58 | FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; |
| 59 | printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); |
| 60 | |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 61 | /* XHCI configuration */ |
| 62 | if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE)) |
| 63 | FchParams_env->Usb.Xhci0Enable = TRUE; |
| 64 | else |
| 65 | FchParams_env->Usb.Xhci0Enable = FALSE; |
| 66 | FchParams_env->Usb.Xhci1Enable = FALSE; |
| 67 | |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 68 | /* SATA configuration */ |
| 69 | FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; |
Richard Spiegel | bb18b43 | 2018-08-03 10:37:28 -0700 | [diff] [blame] | 70 | if (dev && dev->enabled) { |
| 71 | switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { |
| 72 | case SataRaid: |
| 73 | case SataAhci: |
| 74 | case SataAhci7804: |
| 75 | case SataLegacyIde: |
| 76 | FchParams_env->Sata.SataIdeMode = FALSE; |
| 77 | break; |
| 78 | case SataIde2Ahci: |
| 79 | case SataIde2Ahci7804: |
| 80 | default: /* SataNativeIde */ |
| 81 | FchParams_env->Sata.SataIdeMode = TRUE; |
| 82 | break; |
| 83 | } |
| 84 | } else |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 85 | FchParams_env->Sata.SataIdeMode = FALSE; |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 86 | |
| 87 | /* Platform updates */ |
| 88 | platform_FchParams_env(FchParams_env); |
| 89 | |
| 90 | printk(BIOS_DEBUG, "Done\n"); |
| 91 | } |
| 92 | |
| 93 | return AGESA_SUCCESS; |
| 94 | } |
| 95 | |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 96 | AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr) |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 97 | { |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 98 | uint8_t spd_address; |
| 99 | int err; |
| 100 | DEVTREE_CONST struct device *dev; |
| 101 | DEVTREE_CONST struct soc_amd_stoneyridge_config *conf; |
| 102 | AGESA_READ_SPD_PARAMS *info = ConfigPtr; |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 103 | |
| 104 | if (!ENV_ROMSTAGE) |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 105 | return AGESA_UNSUPPORTED; |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 106 | |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 107 | dev = pcidev_path_on_root(DCT_DEVFN); |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 108 | if (dev == NULL) |
| 109 | return AGESA_ERROR; |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 110 | |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 111 | conf = dev->chip_info; |
| 112 | if (conf == NULL) |
| 113 | return AGESA_ERROR; |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 114 | |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 115 | if (info->SocketId >= ARRAY_SIZE(conf->spd_addr_lookup)) |
| 116 | return AGESA_ERROR; |
| 117 | if (info->MemChannelId >= ARRAY_SIZE(conf->spd_addr_lookup[0])) |
| 118 | return AGESA_ERROR; |
| 119 | if (info->DimmId >= ARRAY_SIZE(conf->spd_addr_lookup[0][0])) |
| 120 | return AGESA_ERROR; |
| 121 | |
| 122 | spd_address = conf->spd_addr_lookup |
| 123 | [info->SocketId][info->MemChannelId][info->DimmId]; |
| 124 | if (spd_address == 0) |
| 125 | return AGESA_ERROR; |
| 126 | |
| 127 | err = mainboard_read_spd(spd_address, (void *)info->Buffer, |
| 128 | CONFIG_DIMM_SPD_SIZE); |
| 129 | |
| 130 | /* Read the SPD if the mainboard didn't fill the buffer */ |
| 131 | if (err || (*info->Buffer == 0)) |
| 132 | err = sb_read_spd(spd_address, (void *)info->Buffer, |
| 133 | CONFIG_DIMM_SPD_SIZE); |
| 134 | |
| 135 | if (err) |
| 136 | return AGESA_ERROR; |
| 137 | |
| 138 | return AGESA_SUCCESS; |
| 139 | } |
| 140 | |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 141 | AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) |
Richard Spiegel | a9f4936 | 2018-03-05 08:11:50 -0700 | [diff] [blame] | 142 | { |
| 143 | AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr; |
| 144 | uint32_t flags = 0; |
| 145 | |
| 146 | if (info->PrimaryCore == TRUE) |
| 147 | return AGESA_UNSUPPORTED; /* force normal path */ |
| 148 | if (info->ExecWbinvd == TRUE) |
| 149 | flags |= 1; |
| 150 | if (info->CacheEn == TRUE) |
| 151 | flags |= 2; |
| 152 | |
| 153 | ap_teardown_car(flags); /* does not return */ |
| 154 | |
| 155 | /* Should never reach here */ |
| 156 | return AGESA_UNSUPPORTED; |
| 157 | } |
| 158 | |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 159 | /* Allow mainboards to fill the SPD buffer */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 160 | __weak int mainboard_read_spd(uint8_t spdAddress, char *buf, |
Marc Jones | a9f7277 | 2017-11-16 18:47:36 -0700 | [diff] [blame] | 161 | size_t len) |
| 162 | { |
| 163 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 164 | return -1; /* SPD not read */ |
Martin Roth | c450fbe | 2017-10-02 13:46:50 -0600 | [diff] [blame] | 165 | } |