Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <string.h> |
| 18 | #include <device/pci_def.h> |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 19 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Michał Żygowski | eaba510 | 2018-10-24 16:57:47 +0200 | [diff] [blame] | 21 | #include <device/pnp.h> |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 22 | #include <arch/cpu.h> |
| 23 | #include <cpu/x86/lapic.h> |
| 24 | #include <console/console.h> |
| 25 | #include <commonlib/loglevel.h> |
Michał Żygowski | 57760e3 | 2017-10-17 09:04:58 +0200 | [diff] [blame] | 26 | #include <timestamp.h> |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 27 | #include <cpu/amd/car.h> |
Kyösti Mälkki | bebd766 | 2017-04-13 15:25:43 +0300 | [diff] [blame] | 28 | #include <northbridge/amd/agesa/state_machine.h> |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 29 | #include <northbridge/amd/pi/agesawrapper.h> |
| 30 | #include <northbridge/amd/pi/agesawrapper_call.h> |
| 31 | #include <cpu/x86/bist.h> |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 32 | #include <southbridge/amd/pi/hudson/hudson.h> |
Michał Żygowski | eaba510 | 2018-10-24 16:57:47 +0200 | [diff] [blame] | 33 | #include <superio/nuvoton/common/nuvoton.h> |
| 34 | #include <superio/nuvoton/nct5104d/nct5104d.h> |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 35 | #include <Fch/Fch.h> |
Philipp Deppenwiese | ca39df8 | 2017-03-01 02:37:36 +0100 | [diff] [blame] | 36 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 37 | #include "gpio_ftns.h" |
| 38 | |
Michał Żygowski | eaba510 | 2018-10-24 16:57:47 +0200 | [diff] [blame] | 39 | #define SIO_PORT 0x2e |
| 40 | #define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) |
| 41 | #define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) |
| 42 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 43 | static void early_lpc_init(void); |
| 44 | |
| 45 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 46 | { |
| 47 | u32 val; |
| 48 | |
| 49 | /* |
| 50 | * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for |
| 51 | * LpcClk[1:0]". This following register setting has been |
| 52 | * replicated in every reference design since Parmer, so it is |
| 53 | * believed to be required even though it is not documented in |
| 54 | * the SoC BKDGs. Without this setting, there is no serial |
| 55 | * output. |
| 56 | */ |
| 57 | outb(0xD2, 0xcd6); |
| 58 | outb(0x00, 0xcd7); |
| 59 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 60 | hudson_lpc_port80(); |
| 61 | |
| 62 | if (!cpu_init_detectedx && boot_cpu()) { |
Michał Żygowski | eaba510 | 2018-10-24 16:57:47 +0200 | [diff] [blame] | 63 | pci_devfn_t dev; |
| 64 | u32 data; |
| 65 | |
Michał Żygowski | 57760e3 | 2017-10-17 09:04:58 +0200 | [diff] [blame] | 66 | timestamp_init(timestamp_get()); |
| 67 | timestamp_add_now(TS_START_ROMSTAGE); |
| 68 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 69 | post_code(0x30); |
| 70 | early_lpc_init(); |
| 71 | |
| 72 | hudson_clk_output_48Mhz(); |
| 73 | post_code(0x31); |
Michał Żygowski | eaba510 | 2018-10-24 16:57:47 +0200 | [diff] [blame] | 74 | |
| 75 | dev = PCI_DEV(0, 0x14, 3); |
| 76 | data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 77 | /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ |
| 78 | pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); |
| 79 | |
| 80 | /* COM2 on apu5 is reserved so only COM1 should be supported */ |
| 81 | if ((CONFIG_UART_FOR_CONSOLE == 1) && |
| 82 | !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) |
| 83 | nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); |
| 84 | else if (CONFIG_UART_FOR_CONSOLE == 0) |
| 85 | nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); |
| 86 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 87 | console_init(); |
| 88 | } |
| 89 | |
| 90 | /* Halt if there was a built in self test failure */ |
| 91 | post_code(0x34); |
| 92 | report_bist_failure(bist); |
| 93 | |
| 94 | /* Load MPB */ |
| 95 | val = cpuid_eax(1); |
Elyes HAOUAS | e3e3f4f | 2018-06-29 21:41:41 +0200 | [diff] [blame] | 96 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
| 97 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 98 | |
| 99 | post_code(0x37); |
| 100 | AGESAWRAPPER(amdinitreset); |
| 101 | |
| 102 | post_code(0x38); |
| 103 | printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); |
| 104 | |
| 105 | post_code(0x39); |
| 106 | AGESAWRAPPER(amdinitearly); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 107 | |
Krystian Hebel | fba0320 | 2018-12-21 18:19:14 +0100 | [diff] [blame] | 108 | /* Disable SVI2 controller to wait for command completion */ |
| 109 | val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); |
| 110 | if (val & (1 << 30)) { |
| 111 | printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n"); |
| 112 | } else { |
| 113 | printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n"); |
| 114 | val |= (1 << 30); |
| 115 | pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); |
| 116 | } |
| 117 | |
Michał Żygowski | 57760e3 | 2017-10-17 09:04:58 +0200 | [diff] [blame] | 118 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 119 | |
Kyösti Mälkki | 1b183aa | 2017-02-26 10:11:21 +0200 | [diff] [blame] | 120 | post_code(0x40); |
| 121 | AGESAWRAPPER(amdinitpost); |
Michał Żygowski | 57760e3 | 2017-10-17 09:04:58 +0200 | [diff] [blame] | 122 | |
| 123 | /* FIXME: Detect if TSC frequency changed during raminit? */ |
| 124 | timestamp_rescale_table(1, 4); |
| 125 | |
| 126 | timestamp_add_now(TS_AFTER_INITRAM); |
Kyösti Mälkki | bebd766 | 2017-04-13 15:25:43 +0300 | [diff] [blame] | 127 | } |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 128 | |
Kyösti Mälkki | bebd766 | 2017-04-13 15:25:43 +0300 | [diff] [blame] | 129 | void agesa_postcar(struct sysinfo *cb) |
| 130 | { |
Kyösti Mälkki | 1b183aa | 2017-02-26 10:11:21 +0200 | [diff] [blame] | 131 | //PspMboxBiosCmdDramInfo(); |
| 132 | post_code(0x41); |
| 133 | AGESAWRAPPER(amdinitenv); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 134 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 135 | outb(0xEA, 0xCD6); |
| 136 | outb(0x1, 0xcd7); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 137 | } |
| 138 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 139 | static void early_lpc_init(void) |
| 140 | { |
| 141 | u32 setting = 0x0; |
| 142 | |
| 143 | // |
| 144 | // Configure output disabled, value low, pull up/down disabled |
| 145 | // |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 146 | if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { |
| 147 | configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting); |
| 148 | } |
| 149 | |
Kamil Wcislo | 70b9245 | 2017-10-12 11:55:16 +0200 | [diff] [blame] | 150 | if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) || |
Piotr Król | 83b4fb9 | 2017-11-29 16:34:44 +0100 | [diff] [blame] | 151 | IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) || |
| 152 | IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) { |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 153 | configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); |
Kamil Wcislo | 70b9245 | 2017-10-12 11:55:16 +0200 | [diff] [blame] | 154 | } |
| 155 | |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 156 | configure_gpio(IOMUX_GPIO_49, Function2, GPIO_49, setting); |
| 157 | configure_gpio(IOMUX_GPIO_50, Function2, GPIO_50, setting); |
| 158 | configure_gpio(IOMUX_GPIO_71, Function0, GPIO_71, setting); |
| 159 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 160 | // |
| 161 | // Configure output enabled, value low, pull up/down disabled |
| 162 | // |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 163 | setting = GPIO_OUTPUT_ENABLE; |
Piotr Król | 83b4fb9 | 2017-11-29 16:34:44 +0100 | [diff] [blame] | 164 | if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) || |
| 165 | IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) { |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 166 | configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); |
Kamil Wcislo | 70b9245 | 2017-10-12 11:55:16 +0200 | [diff] [blame] | 167 | } |
| 168 | |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 169 | configure_gpio(IOMUX_GPIO_57, Function1, GPIO_57, setting); |
| 170 | configure_gpio(IOMUX_GPIO_58, Function1, GPIO_58, setting); |
| 171 | configure_gpio(IOMUX_GPIO_59, Function3, GPIO_59, setting); |
| 172 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 173 | // |
| 174 | // Configure output enabled, value high, pull up/down disabled |
| 175 | // |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 176 | setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE; |
| 177 | |
Kamil Wcislo | 70b9245 | 2017-10-12 11:55:16 +0200 | [diff] [blame] | 178 | if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 179 | configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); |
| 180 | configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); |
Kamil Wcislo | 70b9245 | 2017-10-12 11:55:16 +0200 | [diff] [blame] | 181 | } |
| 182 | |
Michał Żygowski | a4432f4 | 2018-07-27 15:59:51 +0200 | [diff] [blame] | 183 | configure_gpio(IOMUX_GPIO_51, Function2, GPIO_51, setting); |
| 184 | configure_gpio(IOMUX_GPIO_55, Function3, GPIO_55, setting); |
| 185 | configure_gpio(IOMUX_GPIO_64, Function2, GPIO_64, setting); |
| 186 | configure_gpio(IOMUX_GPIO_68, Function0, GPIO_68, setting); |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 187 | } |