Blame - src/mainboard/msi/ms7721/buildOpts.c - coreboot

Renze Nicolai

a688b7c

2016-11-18 23:08:13 +0100

[diff] [blame]

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/*

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* This file is part of the coreboot project.

*

*

* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; version 2 of the License.

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*

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

*/

/**

* @file

*

* AMD User options selection for a Brazos platform solution system

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*

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* This file is placed in the user's platform directory and contains the

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* build option selections desired for that platform.

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*

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* For Information about this file, see @ref platforminstall.

*

*/

#include <stdlib.h>

#include <vendorcode/amd/agesa/f15tn/AGESA.h>

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/* Include the files that instantiate the configuration definitions. */

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#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>

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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>

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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>

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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>

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/* the next two headers depend on heapManager.h */

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#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>

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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>

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/* These tables are optional and may be used to adjust memory timing settings */

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#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>

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#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>

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a688b7c

2016-11-18 23:08:13 +0100

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/* Select the CPU family. */

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#define INSTALL_FAMILY_10_SUPPORT FALSE

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#define INSTALL_FAMILY_12_SUPPORT FALSE

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#define INSTALL_FAMILY_14_SUPPORT FALSE

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#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE

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/* Select the CPU socket type. */

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#define INSTALL_G34_SOCKET_SUPPORT FALSE

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#define INSTALL_C32_SOCKET_SUPPORT FALSE

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#define INSTALL_S1G3_SOCKET_SUPPORT FALSE

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#define INSTALL_S1G4_SOCKET_SUPPORT FALSE

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#define INSTALL_ASB2_SOCKET_SUPPORT FALSE

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#define INSTALL_FS1_SOCKET_SUPPORT FALSE

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#define INSTALL_FM1_SOCKET_SUPPORT FALSE

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#define INSTALL_FP2_SOCKET_SUPPORT FALSE

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#define INSTALL_FT1_SOCKET_SUPPORT FALSE

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#define INSTALL_AM3_SOCKET_SUPPORT FALSE

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#define INSTALL_FM2_SOCKET_SUPPORT TRUE

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//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE

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#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE

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#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE

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#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE

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#define BLDOPT_REMOVE_ECC_SUPPORT TRUE

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//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE

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//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE

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#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE

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#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE

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#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE

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//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE

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#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE

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//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE

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#define BLDOPT_REMOVE_SRAT FALSE //TRUE

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#define BLDOPT_REMOVE_SLIT FALSE //TRUE

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#define BLDOPT_REMOVE_WHEA FALSE //TRUE

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#define BLDOPT_REMOVE_CRAT TRUE

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#define BLDOPT_REMOVE_DMI TRUE

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//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE

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//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE

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//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE

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//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE

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//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE

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//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE

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//This element selects whether P-States should be forced to be independent,

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// as reported by the ACPI _PSD object. For single-link processors,

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// setting TRUE for OS to support this feature.

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//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE

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#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS

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#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER

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/* Build configuration values here.

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*/

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#define BLDCFG_VRM_CURRENT_LIMIT 90000

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#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0

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#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0

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#define BLDCFG_PLAT_NUM_IO_APICS 3

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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST

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#define BLDCFG_MEM_INIT_PSTATE 0

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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE

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#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY

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#define BLDCFG_MEMORY_MODE_UNGANGED TRUE

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#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE

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#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED

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#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE

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#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE

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#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE

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#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE

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#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE

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#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE

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#define BLDCFG_MEMORY_POWER_DOWN TRUE

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#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT

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#define BLDCFG_ONLINE_SPARE FALSE

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#define BLDCFG_BANK_SWIZZLE TRUE

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#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO

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#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY

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#define BLDCFG_DQS_TRAINING_CONTROL TRUE

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#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE

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#define BLDCFG_USE_BURST_MODE FALSE

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#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE

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#define BLDCFG_ENABLE_ECC_FEATURE FALSE

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#define BLDCFG_ECC_REDIRECTION FALSE

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#define BLDCFG_SCRUB_DRAM_RATE 0

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#define BLDCFG_SCRUB_L2_RATE 0

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#define BLDCFG_SCRUB_L3_RATE 0

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#define BLDCFG_SCRUB_IC_RATE 0

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#define BLDCFG_SCRUB_DC_RATE 0

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#define BLDCFG_ECC_SYMBOL_SIZE 4

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#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000

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#define BLDCFG_ECC_SYNC_FLOOD FALSE

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#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE

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#define BLDCFG_1GB_ALIGN FALSE

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#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE

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#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%

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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770

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#define BLDOPT_REMOVE_ALIB FALSE

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#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled

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#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'

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#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'

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#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6

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#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200

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#define BLDCFG_CFG_ABM_SUPPORT 0

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//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770

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// Specify the default values for the VRM controlling the VDDNB plane.

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// If not specified, the values used for the core VRM will be applied

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//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity

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//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L

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//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime

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//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity

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//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity

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//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity

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#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000

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#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3

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#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3

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Martin Roth

43927ba

2017-06-24 21:54:33 -0600

[diff] [blame]

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#if IS_ENABLED(CONFIG_GFXUMA)

Elyes HAOUAS

1d44634

2018-05-28 13:41:43 +0200

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#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED

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#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED

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e3e3f4f

2018-06-29 21:41:41 +0200

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//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/

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#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M

Elyes HAOUAS

1d44634

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#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE

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a688b7c

2016-11-18 23:08:13 +0100

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#endif

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#define BLDCFG_IOMMU_SUPPORT TRUE

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#define BLDCFG_CFG_GNB_HD_AUDIO TRUE

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//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID

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//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID

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//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID

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/* Process the options...

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* This file include MUST occur AFTER the user option selection settings

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*/

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/*

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* Customized OEM build configurations for FCH component

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*/

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// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00

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// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20

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// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00

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// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400

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// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404

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// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408

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// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410

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// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420

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// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000

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// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000

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// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000

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// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0

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// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00

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// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000

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// #define BLDCFG_AZALIA_SSID 0x780D1022

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// #define BLDCFG_SMBUS_SSID 0x780B1022

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// #define BLDCFG_IDE_SSID 0x780C1022

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// #define BLDCFG_SATA_AHCI_SSID 0x78011022

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// #define BLDCFG_SATA_IDE_SSID 0x78001022

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// #define BLDCFG_SATA_RAID5_SSID 0x78031022

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// #define BLDCFG_SATA_RAID_SSID 0x78021022

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// #define BLDCFG_EHCI_SSID 0x78081022

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// #define BLDCFG_OHCI_SSID 0x78071022

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// #define BLDCFG_LPC_SSID 0x780E1022

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// #define BLDCFG_SD_SSID 0x78061022

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// #define BLDCFG_XHCI_SSID 0x78121022

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// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE

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// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE

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// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4

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// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE

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// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE

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// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE

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// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE

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// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE

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// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE

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// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE

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// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE

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CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =

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{

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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },

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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },

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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },

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{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },

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{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },

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{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },

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{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },

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{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },

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{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },

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{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },

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{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },

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{ CPU_LIST_TERMINAL }

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};

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#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList

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// This is the delivery package title, "BrazosPI"

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// This string MUST be exactly 8 characters long

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#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}

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// This is the release version number of the AGESA component

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// This string MUST be exactly 12 characters long

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#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}

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/* MEMORY_BUS_SPEED */

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#define DDR400_FREQUENCY 200 ///< DDR 400

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#define DDR533_FREQUENCY 266 ///< DDR 533

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#define DDR667_FREQUENCY 333 ///< DDR 667

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#define DDR800_FREQUENCY 400 ///< DDR 800

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#define DDR1066_FREQUENCY 533 ///< DDR 1066

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#define DDR1333_FREQUENCY 667 ///< DDR 1333

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#define DDR1600_FREQUENCY 800 ///< DDR 1600

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#define DDR1866_FREQUENCY 933 ///< DDR 1866

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#define DDR2100_FREQUENCY 1050 ///< DDR 2100

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#define DDR2133_FREQUENCY 1066 ///< DDR 2133

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#define DDR2400_FREQUENCY 1200 ///< DDR 2400

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#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency

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/* QUANDRANK_TYPE*/

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#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM

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#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM

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/* USER_MEMORY_TIMING_MODE */

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#define TIMING_MODE_AUTO 0 ///< Use best rate possible

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#define TIMING_MODE_LIMITED 1 ///< Set user top limit

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#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed

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/* POWER_DOWN_MODE */

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#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode

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#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode

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/*

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* Agesa optional capabilities selection.

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* Uncomment and mark FALSE those features you wish to include in the build.

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* Comment out or mark TRUE those features you want to REMOVE from the build.

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*/

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#define DFLT_SMBUS0_BASE_ADDRESS 0xB00

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#define DFLT_SMBUS1_BASE_ADDRESS 0xB20

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/* The AGESA likes to enable 512 bytes region on this base for LPC bus */

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#define DFLT_SIO_PME_BASE_ADDRESS 0xE00

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#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800

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#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804

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#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808

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#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810

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#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820

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#define DFLT_SPI_BASE_ADDRESS 0xFEC10000

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#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0

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#define DFLT_HPET_BASE_ADDRESS 0xFED00000

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#define DFLT_SMI_CMD_PORT 0xB0

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#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00

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#define DFLT_GEC_BASE_ADDRESS 0xFED61000

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#define DFLT_AZALIA_SSID 0x780D1022

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#define DFLT_SMBUS_SSID 0x780B1022

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#define DFLT_IDE_SSID 0x780C1022

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#define DFLT_SATA_AHCI_SSID 0x78011022

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#define DFLT_SATA_IDE_SSID 0x78001022

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#define DFLT_SATA_RAID5_SSID 0x78031022

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#define DFLT_SATA_RAID_SSID 0x78021022

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#define DFLT_EHCI_SSID 0x78081022

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#define DFLT_OHCI_SSID 0x78071022

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#define DFLT_LPC_SSID 0x780E1022

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#define DFLT_SD_SSID 0x78061022

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#define DFLT_XHCI_SSID 0x78121022

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#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE

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#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE

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#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1

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#define DFLT_FCH_GPP_PORT0_PRESENT TRUE

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#define DFLT_FCH_GPP_PORT1_PRESENT TRUE

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#define DFLT_FCH_GPP_PORT2_PRESENT FALSE

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#define DFLT_FCH_GPP_PORT3_PRESENT FALSE

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#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE

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#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE

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#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE

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#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE

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//#define BLDCFG_IR_PIN_CONTROL 0x33

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//#define FCH_NO_XHCI_SUPPORT FALSE

Renze Nicolai

282c832

2016-11-18 23:33:16 +0100

[diff] [blame]

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GPIO_CONTROL ms7721_m_gpio[] = {

Renze Nicolai

a688b7c

2016-11-18 23:08:13 +0100

[diff] [blame]

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// {183, Function1, PullUpB},

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{-1}

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};

Renze Nicolai

282c832

2016-11-18 23:33:16 +0100

[diff] [blame]

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#define BLDCFG_FCH_GPIO_CONTROL_LIST (&ms7721_m_gpio[0])

Renze Nicolai

a688b7c

2016-11-18 23:08:13 +0100

[diff] [blame]

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// The following definitions specify the default values for various parameters in which there are

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// no clearly defined defaults to be used in the common file. The values below are based on product

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// and BKDG content, please consult the AGESA Memory team for consultation.

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#define DFLT_SCRUB_DRAM_RATE (0)

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#define DFLT_SCRUB_L2_RATE (0)

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#define DFLT_SCRUB_L3_RATE (0)

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#define DFLT_SCRUB_IC_RATE (0)

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#define DFLT_SCRUB_DC_RATE (0)

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#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED

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#define DFLT_VRM_SLEW_RATE (5000)

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/* Moving this include up will break AGESA. */

Kyösti Mälkki

c8e4742

2017-08-31 08:52:12 +0300

[diff] [blame]

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#include <PlatformInstall.h>