Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
Renze Nicolai | 282c832 | 2016-11-18 23:33:16 +0100 | [diff] [blame] | 5 | * Copyright (C) 2016 Renze Nicolai <renze@rnplus.nl> |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 17 | #include <Porting.h> |
| 18 | #include <AGESA.h> |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 19 | |
Kyösti Mälkki | a84e34b | 2017-03-04 07:34:08 +0200 | [diff] [blame] | 20 | #include <northbridge/amd/agesa/state_machine.h> |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 21 | #include <PlatformMemoryConfiguration.h> |
| 22 | |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 23 | |
| 24 | /* |
| 25 | * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) |
| 26 | * |
| 27 | * Lane Id |
| 28 | * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 |
| 29 | * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 |
| 30 | * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 |
| 31 | * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 |
| 32 | * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 |
| 33 | * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 |
| 34 | * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 |
| 35 | * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 |
| 36 | * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI |
| 37 | * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI |
| 38 | * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI |
| 39 | * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI |
| 40 | * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI |
| 41 | * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI |
| 42 | * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI |
| 43 | * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI |
| 44 | * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI |
| 45 | * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI |
| 46 | * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI |
| 47 | * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI |
| 48 | * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI |
| 49 | * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI |
| 50 | * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI |
| 51 | * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI |
| 52 | * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) |
| 53 | * 25 DP0_TX[P,N]1 |
| 54 | * 26 DP0_TX[P,N]2 |
| 55 | * 27 DP0_TX[P,N]3 |
| 56 | * 28 DP1_TX[P,N]0 |
| 57 | * 29 DP1_TX[P,N]1 |
| 58 | * 30 DP1_TX[P,N]2 |
| 59 | * 31 DP1_TX[P,N]3 |
| 60 | * 32 DP2_TX[P,N]0 |
| 61 | * 33 DP2_TX[P,N]1 |
| 62 | * 34 DP2_TX[P,N]2 |
| 63 | * 35 DP2_TX[P,N]3 |
| 64 | * 36 DP2_TX[P,N]4 |
| 65 | * 37 DP2_TX[P,N]5 |
| 66 | * 38 DP2_TX[P,N]6 |
| 67 | */ |
| 68 | |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 69 | static const PCIe_PORT_DESCRIPTOR PortList[] = { |
Renze Nicolai | 282c832 | 2016-11-18 23:33:16 +0100 | [diff] [blame] | 70 | /* PCIe port, Lanes 8:23, PCI Device Number 2, x16 slot */ |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 71 | { |
| 72 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 73 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), |
Kyösti Mälkki | 9fee35c | 2017-09-23 19:10:04 +0300 | [diff] [blame] | 74 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, |
| 75 | HotplugDisabled, |
| 76 | PcieGenMaxSupported, |
| 77 | PcieGenMaxSupported, |
| 78 | AspmDisabled, 1) |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 79 | }, |
Renze Nicolai | 282c832 | 2016-11-18 23:33:16 +0100 | [diff] [blame] | 80 | /* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */ |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 81 | { |
| 82 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 83 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), |
Kyösti Mälkki | 9fee35c | 2017-09-23 19:10:04 +0300 | [diff] [blame] | 84 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, |
| 85 | HotplugDisabled, |
| 86 | PcieGenMaxSupported, |
| 87 | PcieGenMaxSupported, |
| 88 | AspmDisabled, 1) |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 89 | }, |
Renze Nicolai | 282c832 | 2016-11-18 23:33:16 +0100 | [diff] [blame] | 90 | /* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */ |
| 91 | { |
| 92 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 93 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), |
Kyösti Mälkki | 9fee35c | 2017-09-23 19:10:04 +0300 | [diff] [blame] | 94 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, |
| 95 | HotplugDisabled, |
| 96 | PcieGenMaxSupported, |
| 97 | PcieGenMaxSupported, |
| 98 | AspmDisabled, 1) |
Renze Nicolai | 282c832 | 2016-11-18 23:33:16 +0100 | [diff] [blame] | 99 | }, |
| 100 | /* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */ |
| 101 | { |
| 102 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 103 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), |
Kyösti Mälkki | 9fee35c | 2017-09-23 19:10:04 +0300 | [diff] [blame] | 104 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, |
| 105 | HotplugDisabled, |
| 106 | PcieGenMaxSupported, |
| 107 | PcieGenMaxSupported, |
| 108 | AspmDisabled, 1) |
Renze Nicolai | 282c832 | 2016-11-18 23:33:16 +0100 | [diff] [blame] | 109 | }, |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 110 | /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ |
| 111 | { |
| 112 | DESCRIPTOR_TERMINATE_LIST, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 113 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), |
Kyösti Mälkki | 9fee35c | 2017-09-23 19:10:04 +0300 | [diff] [blame] | 114 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, |
| 115 | HotplugDisabled, |
| 116 | PcieGenMaxSupported, |
| 117 | PcieGenMaxSupported, |
| 118 | AspmDisabled, 0) |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 119 | }, |
| 120 | }; |
| 121 | |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 122 | static const PCIe_DDI_DESCRIPTOR DdiList[] = { |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 123 | // DP0 to HDMI0/DP |
| 124 | { |
| 125 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 126 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), |
| 127 | PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 128 | }, |
| 129 | // DP1 to FCH |
| 130 | { |
| 131 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 132 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), |
| 133 | PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 134 | }, |
| 135 | // DP2 to HDMI1/DP |
| 136 | { |
| 137 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 138 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), |
| 139 | PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 140 | }, |
| 141 | }; |
| 142 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 143 | static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { |
| 144 | .Flags = DESCRIPTOR_TERMINATE_LIST, |
| 145 | .SocketId = 0, |
| 146 | .PciePortList = PortList, |
| 147 | .DdiLinkList = DdiList, |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 148 | }; |
| 149 | |
Kyösti Mälkki | a84e34b | 2017-03-04 07:34:08 +0200 | [diff] [blame] | 150 | void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) |
| 151 | { |
| 152 | FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; |
| 153 | FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); |
| 154 | FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); |
| 155 | } |
| 156 | |
Kyösti Mälkki | a84e34b | 2017-03-04 07:34:08 +0200 | [diff] [blame] | 157 | void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 158 | { |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 159 | InitEarly->GnbConfig.PcieComplexList = &PcieComplex; |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | /*---------------------------------------------------------------------------------------- |
| 163 | * CUSTOMER OVERIDES MEMORY TABLE |
| 164 | *---------------------------------------------------------------------------------------- |
| 165 | */ |
| 166 | |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 167 | /* |
| 168 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA |
| 169 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable |
| 170 | * is populated, AGESA will base its settings on the data from the table. Otherwise, it will |
| 171 | * use its default conservative settings. |
| 172 | */ |
Kyösti Mälkki | a84e34b | 2017-03-04 07:34:08 +0200 | [diff] [blame] | 173 | static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 174 | |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 175 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), |
| 176 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 177 | /* |
| 178 | TODO: is this OK for DDR3 socket FM2? |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 179 | MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), |
| 180 | CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), |
| 181 | ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), |
| 182 | CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 183 | */ |
| 184 | PSO_END |
| 185 | }; |
Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 186 | |
Kyösti Mälkki | a84e34b | 2017-03-04 07:34:08 +0200 | [diff] [blame] | 187 | |
| 188 | void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) |
| 189 | { |
| 190 | InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; |
| 191 | } |
| 192 | |
| 193 | void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) |
| 194 | { |
| 195 | /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ |
| 196 | InitMid->GnbMidConfiguration.iGpuVgaMode = 0; |
| 197 | } |