Tobias Diedrich | 7a95204 | 2017-12-03 10:09:28 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Vladimir Serbinenko |
| 6 | * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <halt.h> |
| 21 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Tobias Diedrich | 7a95204 | 2017-12-03 10:09:28 +0100 | [diff] [blame] | 23 | #include <device/pci_def.h> |
Tobias Diedrich | 7a95204 | 2017-12-03 10:09:28 +0100 | [diff] [blame] | 24 | #include <console/console.h> |
Elyes HAOUAS | 4ad1446 | 2018-06-16 18:29:33 +0200 | [diff] [blame] | 25 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 26 | |
Tobias Diedrich | 7a95204 | 2017-12-03 10:09:28 +0100 | [diff] [blame] | 27 | #include "superio.h" |
| 28 | #include "thermal.h" |
| 29 | |
| 30 | #if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) |
| 31 | #define DEBUG_UART_EN 0 |
| 32 | #else |
| 33 | #define DEBUG_UART_EN COMA_LPC_EN |
| 34 | #endif |
| 35 | |
| 36 | void pch_enable_lpc(void) |
| 37 | { |
| 38 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, |
| 39 | CNF2_LPC_EN | DEBUG_UART_EN); |
| 40 | /* Decode SuperIO 0x0a00 */ |
| 41 | pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01); |
| 42 | } |
| 43 | |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 44 | void mainboard_rcba_config(void) |
Tobias Diedrich | 7a95204 | 2017-12-03 10:09:28 +0100 | [diff] [blame] | 45 | { |
| 46 | /* Disable devices */ |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 47 | RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; |
Tobias Diedrich | 7a95204 | 2017-12-03 10:09:28 +0100 | [diff] [blame] | 48 | |
| 49 | #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) |
| 50 | /* Enable Gigabit Ethernet */ |
| 51 | if (RCBA32(BUC) & PCH_DISABLE_GBE) { |
| 52 | RCBA32(BUC) &= ~PCH_DISABLE_GBE; |
| 53 | /* Datasheet says clearing the bit requires a reset after */ |
| 54 | printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n"); |
| 55 | outb(0xe, 0xcf9); |
| 56 | halt(); |
| 57 | } |
| 58 | #endif |
| 59 | |
| 60 | /* Set "mobile" bit in MCH (which makes sense layout-wise). */ |
| 61 | /* Note sure if this has any effect at all though. */ |
| 62 | MCHBAR32(0x0004) |= 0x00001000; |
| 63 | MCHBAR32(0x0104) |= 0x00001000; |
| 64 | } |
| 65 | |
| 66 | void mainboard_early_init(int s3resume) |
| 67 | { |
| 68 | } |
| 69 | |
| 70 | static const u16 hwm_initvals[] = { |
| 71 | HWM_BANK(0), |
| 72 | HWM_INITVAL(0xae, 0x01), /* Enable PECI Agent0 */ |
| 73 | |
| 74 | HWM_BANK(7), /* PECI */ |
| 75 | HWM_INITVAL(0x01, 0x95), /* Enable PECI */ |
| 76 | HWM_INITVAL(0x03, 0x10), /* Enable Agent 0 */ |
| 77 | /* |
| 78 | * PECI temperatures are negative, going up to 0. |
| 79 | * 0 represents the maximum allowable junction temperature, Tjmax. |
| 80 | * There is also Tcontrol, which is the temperature at which the |
| 81 | * system cooling should run at full speed. |
| 82 | * Since the NCT5577D fan control only supports positive values, |
| 83 | * Tbase0 is used as an offset. |
| 84 | */ |
| 85 | HWM_INITVAL(0x09, CRITICAL_TEMPERATURE), /* Tbase0 */ |
| 86 | |
| 87 | HWM_BANK(2), /* CPUFAN control */ |
| 88 | HWM_INITVAL(0x00, 0x0c), /* PECI Agent 0 as CPUFAN monitoring source */ |
| 89 | HWM_INITVAL(0x01, 50), /* Target temperature */ |
| 90 | HWM_INITVAL(0x02, 0x40), /* Enable Smart Fan IV mode */ |
| 91 | HWM_INITVAL(0x03, 0x01), /* Step-up time */ |
| 92 | HWM_INITVAL(0x04, 0x01), /* Step-down time */ |
| 93 | HWM_INITVAL(0x05, 0x10), /* Stop PWM value */ |
| 94 | HWM_INITVAL(0x06, 0x20), /* Start PWM value */ |
| 95 | HWM_INITVAL(0x21, 45), /* Smart Fan IV Temp1 */ |
| 96 | HWM_INITVAL(0x22, 46), /* Smart Fan IV Temp2 */ |
| 97 | HWM_INITVAL(0x23, 47), /* Smart Fan IV Temp3 */ |
| 98 | HWM_INITVAL(0x24, PASSIVE_TEMPERATURE), /* Smart Fan IV Temp4 */ |
| 99 | HWM_INITVAL(0x27, 0x01), /* Smart Fan IV PWM1 */ |
| 100 | HWM_INITVAL(0x28, 0x02), /* Smart Fan IV PWM2 */ |
| 101 | HWM_INITVAL(0x29, 0x03), /* Smart Fan IV PWM3 */ |
| 102 | HWM_INITVAL(0x2a, 0xff), /* Smart Fan IV PWM4 */ |
| 103 | /* Smart Fan IV Critical temp */ |
| 104 | HWM_INITVAL(0x35, CRITICAL_TEMPERATURE), |
| 105 | HWM_INITVAL(0x38, 3), /* Smart Fan IV Critical temp tolerance */ |
| 106 | HWM_INITVAL(0x39, 0x81), /* Enable SYSTIN weight value */ |
| 107 | HWM_INITVAL(0x3a, 1), /* SYSTIN temperature step */ |
| 108 | HWM_INITVAL(0x3b, 2), /* SYSTIN step tolerance */ |
| 109 | HWM_INITVAL(0x3c, 1), /* SYSTIN weight step */ |
| 110 | HWM_INITVAL(0x3d, 40), /* SYSTIN temperature base */ |
| 111 | HWM_INITVAL(0x3e, 0x00), /* SYSTIN fan duty base */ |
| 112 | |
| 113 | HWM_BANK(0), |
| 114 | }; |
| 115 | |
| 116 | static void hwm_init(void) |
| 117 | { |
| 118 | /* Set up fan control */ |
| 119 | for (int i = 0; i < ARRAY_SIZE(hwm_initvals); i++) |
| 120 | HWM_WRITE_INITVAL(hwm_initvals[i]); |
| 121 | } |
| 122 | |
| 123 | static const u16 superio_initvals[] = { |
| 124 | /* Global config registers */ |
| 125 | SUPERIO_INITVAL(0x1a, 0x02), |
| 126 | SUPERIO_INITVAL(0x1b, 0x6a), |
| 127 | SUPERIO_INITVAL(0x27, 0x80), |
| 128 | #if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) |
| 129 | SUPERIO_INITVAL(0x2a, 0x80), |
| 130 | #else |
| 131 | SUPERIO_INITVAL(0x2a, 0x00), |
| 132 | #endif |
| 133 | SUPERIO_INITVAL(0x2c, 0x00), |
| 134 | |
| 135 | SUPERIO_BANK(2), /* UART A */ |
| 136 | SUPERIO_INITVAL(0x30, 0x01), |
| 137 | SUPERIO_INITVAL(0x60, 0x03), |
| 138 | SUPERIO_INITVAL(0x61, 0xf8), |
| 139 | SUPERIO_INITVAL(0x70, 0x04), |
| 140 | |
| 141 | SUPERIO_BANK(7), /* GPIO config */ |
| 142 | SUPERIO_INITVAL(0x30, 0x01), |
| 143 | SUPERIO_INITVAL(0xe0, 0xcf), |
| 144 | SUPERIO_INITVAL(0xe1, 0x0f), |
| 145 | SUPERIO_INITVAL(0xe4, 0xed), |
| 146 | SUPERIO_INITVAL(0xe5, 0x4d), |
| 147 | SUPERIO_INITVAL(0xec, 0x30), |
| 148 | SUPERIO_INITVAL(0xee, 0xff), |
| 149 | |
| 150 | SUPERIO_BANK(8), |
| 151 | SUPERIO_INITVAL(0x30, 0x0a), |
| 152 | SUPERIO_INITVAL(0x60, GPIO_PORT >> 8), |
| 153 | SUPERIO_INITVAL(0x61, GPIO_PORT & 0xff), |
| 154 | |
| 155 | SUPERIO_BANK(9), |
| 156 | SUPERIO_INITVAL(0x30, 0x8c), |
| 157 | SUPERIO_INITVAL(0xe1, 0x90), |
| 158 | |
| 159 | SUPERIO_BANK(0xa), |
| 160 | SUPERIO_INITVAL(0xe4, 0x20), |
| 161 | SUPERIO_INITVAL(0xe6, 0x4c), |
| 162 | |
| 163 | SUPERIO_BANK(0xb), /* HWM & LED */ |
| 164 | SUPERIO_INITVAL(0x30, 0x01), |
| 165 | SUPERIO_INITVAL(0x60, HWM_PORT >> 8), |
| 166 | SUPERIO_INITVAL(0x61, HWM_PORT & 0xff), |
| 167 | SUPERIO_INITVAL(0xf7, 0x67), |
| 168 | SUPERIO_INITVAL(0xf8, 0x60), |
| 169 | |
| 170 | SUPERIO_BANK(0x16), |
| 171 | SUPERIO_INITVAL(0x30, 0x00), |
| 172 | }; |
| 173 | |
| 174 | static void superio_init(void) |
| 175 | { |
| 176 | SUPERIO_UNLOCK; |
| 177 | for (int i = 0; i < ARRAY_SIZE(superio_initvals); i++) |
| 178 | SUPERIO_WRITE_INITVAL(superio_initvals[i]); |
| 179 | SUPERIO_LOCK; |
| 180 | } |
| 181 | |
| 182 | void mainboard_config_superio(void) |
| 183 | { |
| 184 | superio_init(); |
| 185 | hwm_init(); |
| 186 | } |
| 187 | |
| 188 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 189 | { |
| 190 | read_spd(&spd[0], 0x50, id_only); |
| 191 | read_spd(&spd[2], 0x51, id_only); |
| 192 | } |
| 193 | |
| 194 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 195 | #define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin } |
| 196 | #include "usb.h" |
| 197 | }; |